|
Loading... E:\allegroXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstchip.dat
' A2 R) j+ k4 q+ V3 b# Q
* d5 L4 s- O0 }+ @Loading... E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstchip.dat7 w+ ~! K9 Q/ P* l% E: }) {4 \
, _1 y$ p1 z+ u0 q8 rLoading... E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstxprt.dat
" k; c* P3 Z8 ]* j# |' g. i- E9 V#77 ERROR(SPCODD-77): Could not open file E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstxprt.dat.
8 J [* Q1 N/ y, A5 _! B' c& uYou might be trying to reuse a design with an inaccessible state file. To reuse a design, ensure that the design being reused is treated as a subdesign and the subdesign state file is accessible and readable. To create the subdesign state file, use the GEN_SUBDESIGN directive.
# d4 L0 k' O3 w: ~1 v1 V* M8 R) K; WERROR(SPCODD-382): Error at line 1 in file E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstxprt.dat. Error loading the parts list file/ F, ?' B- y' {* S0 U, _
. w5 f6 i0 E& k% Z' Y" V1 J#292 ERROR(ORCAP-36026): Unable to read logical netlist data.- b: H7 n- { F; p+ o9 Z P* z7 j/ V
1 H9 L, f/ g: u1 |% }( T
$ X) `) i& E' @/ E) y& D1 _( eorcad在导网表时出现打不开pstxprt.dat文件,在Allegro文件下不能找到该文件,不知道为什么没有生成,恳请大佬帮助一下。3 q' t# k0 T6 x, b
* ~ y" @+ s/ U2 r$ [ |
|