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发表于 2023-4-3 18:30:57
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Switch mode regulators
0 i) i6 e% ]& s% h/ z; LQCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
5 ~5 v9 h4 ^+ Ereceive power from VBAT or VCHG under application software control.
# c4 c. U7 V9 s! vThe System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040
) g+ |3 L! C6 v2 W6 C# v+ r/ wVFBGA and the flash memory. The System SMPS can supply power to external components.
( ~3 f' j0 `8 Q) h+ c# t0 z' B* W/ NThe digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches
. J y5 B- o! N5 Qbetween 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
T! x1 I! W$ LThe SMPS both have three operating modes:3 [1 C: @0 q0 P( Y
■ Normal (PWM)
/ o! A7 x& f; g, U: @: N& t0 }6 p) T& I■ Two low-power modes with reduced current capability:
6 k: J3 r! R% G9 q/ Z□ PFM
( n1 m7 ?1 p$ h' O) v7 g8 _□ ULP4 R, _; m2 G- E2 T; g7 i1 s$ A
Normally the system auto switches, but this is optionally disabled.
3 f$ x3 [( `2 t4 L' DThe SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.8 ~/ g* i# }2 v5 Z0 P
For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-2 \$ b/ R$ o# p5 [! Z& o7 }4 `$ k
CH285-1).
' `& w, r' J. [' Q. ]* \A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have
! Z7 n) P- ^5 m' ~+ {0 X% ta 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.. c8 J' z$ j& p' s! X
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
; C0 n9 S; k" k( }% t& N) Q1 [. r
& o7 h2 r* |9 z- k: k |
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