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27号补丁修复的BUG较多！
' ]4 K; @6 w& z+ E0 @百度网盘下载链接http://pan.baidu.com/s/1mgwSsPy
4 T1 U- M. Z5 Q$ ?& z+ Z+ N# O9 F& F
DATE: 04-25-2014 HOTFIX VERSION: 027
5 k. q, V @ N; V===================================================================================================================================
' }1 B; q, l. D3 m0 S! MCCRID PRODUCT PRODUCTLEVEL2 TITLE
$ q1 A* C4 ?; f( \===================================================================================================================================3 O3 W9 G; t+ v/ V6 I k! t3 t
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM/ _ N8 N. r O* o& y
481674 allegro_EDITOR pads_IN No board file saved from pads_in
; O4 c' H6 [, r; b M% C( m2 E982929 allegro_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.( V) K" b: @5 q$ P+ G! J8 w5 Q
1012783 FSP OTHER Need Undo Command in FSP% W2 y2 u7 R$ x" G I+ F
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
5 S, k/ y5 n' Z9 ]+ G% d* J5 k1072673 pcb_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved5 K4 L, X5 b. M# n5 A5 N1 @
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.; U @1 e* E( e' V
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
6 ~8 E5 B. @9 h& I& L1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
7 o0 c) O9 _/ A$ w* {1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command) P) `% K, r9 |' F/ }
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode y- W" `. `) y; `
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present) X" b3 ^" V1 b! q4 I0 n
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
" @. ]* {3 W2 q3 s5 j1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings% g! D6 t9 T# R. V9 f
1185575 SIP_layout DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.3 ]$ f& Q3 D$ O! u* c
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV; U% {8 w- _; `. {% e% m
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part." Z$ a- {6 D0 [. l
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates: ~+ g. X; ]. a5 \1 ~
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
' T* h, j. f% C5 ^. | `6 M& p$ S+ f1208478 PSPICE PROBE Attached project gives overflow error with marching ON.. `( z% c* v# f
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol: L$ V3 B7 C6 J- ?) `" y6 c
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed( K9 A, K' R9 s$ u- W& {) {3 F( Z; ?
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
# A% Y z" u) j4 o: _1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
7 Q9 N8 R5 O0 `/ x( r4 Z6 J1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?+ g2 B( v/ Z$ Q. M+ _& G) f1 \
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
+ ? x* A' e( F- W' D1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
) }7 c8 B5 _8 M% v7 M1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging$ j7 N. Q' _: k" e0 C
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
: s2 W0 Y. J& [1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added' a5 A; F |0 X _0 P* K
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
8 f: R- z) ]. ^9 X1 _& K1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
4 X, ~ m5 s& s, _9 h) |; N# c1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux. L, w8 m7 [. U
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided., r, E, f* \: o' D' L. \! t1 H
1221182 ADW TDA Team Design with SAMBA' S7 m4 x( Z+ X! Z* Z) e) w' `. A
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
9 r# D; h0 W5 [9 R$ b% B9 _1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened7 C- \- r* @: C
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?! r# M3 F$ I. |& O2 m
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
, ?$ o+ a- i8 m1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
9 v6 Y& l( Z7 x% f6 K7 D1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version." a% @2 U/ d4 ~$ F& d: p. d. \, f
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor- f2 U& C2 C; P3 w4 |" w
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines." P \' c! l7 K9 g9 g# H( w
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
6 i+ e4 b" Y. X" X; O1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
% g+ `0 w+ D7 l" h1 ]; v7 }# J1225494 CAPTURE DRC Different DRC results for Entire design and selection: f; T( L" N0 v: U$ b; x
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
0 R% R, V2 w( Z* a! H) q/ Q1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
( z' N/ t2 o# l: M1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
3 m. G0 I% v. x( l- }( y1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal% c) ^/ q( z8 W% D; x
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file( t" c9 x' {: d6 l6 b" u1 ~% S
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors3 `! o5 T* I7 y9 i2 ]$ u
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
8 r0 R" }1 d" o7 ?; h9 A1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
4 N3 g. l) L6 X" Q3 n1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
' W) G- c9 i& i0 x1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case% ?/ D! [# a, F! S
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
* ]) t, K" S+ }1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
% y0 E. G6 Q& F, b& U3 g( i1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
4 h) [- f y- r5 p& I4 n$ \1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
# e' x4 a8 e3 S7 o% t' h1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
8 P* G( ?. ^/ V3 s1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
- V: k$ a) z9 g" b1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
# i+ h9 Z$ ?. L$ ~0 W1230432 CONCEPT_HDL CORE No Description information in BOM6 q5 ~$ R* [/ n/ W
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
- c7 r/ x' |. z" j1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files% L: k/ b2 h2 S2 l2 E; t9 p
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands9 Z& Z4 A0 z+ T$ L, W' F3 ?
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
) S- p; A1 |& a7 R0 ^3 |1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.! _, Y. E8 x# u6 b- { e
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode( T/ o1 \# {. D7 _, L6 G% b. m
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
3 E, }, n. i. P# f \" Y1 H1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode2 U U' @: f: b! K+ P! B3 k
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
: [% U7 }: p7 _8 S* n+ r4 y1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
: r, z# I# M; q- y" S V" [6 B1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
1 y1 c- n3 g# |( H( @: o4 ?1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect# ~8 v+ s/ h/ D! v( a. W
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
' D+ g( i& u7 _7 e8 K a4 @& v! x9 H1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic: u0 _' _: W! P4 r# |
1236161 CONCEPT_HDL CORE Import Design shows the current project pages
& m) {2 F! e9 ]4 w* X1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.( }/ @; H( t# w# B Q1 K
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
) J3 L! S2 \) z4 Q+ {1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
. c* P- M. l% Z/ M; K: e1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape! x1 d+ q& ]8 g6 L
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming4 n% x/ c4 N) d8 y) X
1236781 F2B PACKAGERXL Export Physical produces empty files) `; V+ ?. [7 Y+ s! ^& }' H
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run+ L/ M! w0 r, r7 R
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command$ P6 f% ^* [, U: y5 m. }/ {1 v# @
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition' O7 Y, u8 W% o( N6 n
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
2 ~* J. U, R" W3 T1238852 CAPTURE GENERAL signal list not updated for buses1 d& O/ g8 m6 h0 Q
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
. P% a3 l3 H3 P% E4 `* I7 [1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
, @+ c- ~+ C9 R7 v: \# _, `1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
: S; A( U+ t9 C) Q0 G( i1239763 PSPICE PROBE Cannot modify text label if right y axis is active: N" N$ B+ a1 V- J; d, S
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images% O, x9 ]( d( l" U" w
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture./ U9 R/ b; f6 x/ o: Q
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
# d; Y% F9 h5 [" h$ U& q) A% ]1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
5 y6 {; f6 W1 G. g8 D1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable$ C- ?, p) D% p7 c w) c: O
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy" N5 `1 a6 ]/ [4 K# k" u
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms& q" L( t& u# w* N( _- z
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
" i& h8 w1 Q, ~! A: }9 t1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.. N- }* P% Z3 Z2 P
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard! \% M$ E; H5 M- E
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
4 k0 B% p4 a: _. \/ ?# O3 n" g1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side; v7 d4 Q/ Y$ E/ V
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer+ ~5 Z: I3 |3 Y5 H, r# C3 [
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results5 d9 `* f% B3 V" H. V" Y/ F
1243609 CONCEPT_HDL CORE autoprop for occurrence properties
1 u% E# I" w2 j- t K4 g8 I, `. d1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
" |* z" w& p4 x. H+ h+ A- S1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed., I- W( r' D- f, M* {# G
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
0 B" A/ d5 @2 |4 j7 C1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
- k) T& }. E: C5 x1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is1 \: }! C+ m/ P7 G# n) e) H
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
5 _+ P1 X2 P8 O1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
) H9 g9 L8 e# v) E! o F9 p1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character. y' B" o1 Q- @3 `0 @8 S! e
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
% {* L' g' a2 b1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown/ C$ X3 l9 J' z
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
: U+ \6 g8 X# W; X1 H7 y8 e1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL: w6 p1 x8 o: \' C) t9 f
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
9 u! m. S, v! u+ n! s* @1247462 CONCEPT_HDL CORE Text issue while moving with bounding box3 j8 l% @% i. J) n+ F+ L
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
3 [$ x8 d5 ?" g. u8 U/ n1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components( ^7 V! M6 [. n. U# z; |8 n' v e/ q
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts; Y2 z7 i: F' |" h' U, ^
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
9 ?3 B1 Y* B8 B/ L5 Z3 ]1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint! k w( g m. Q) c& n' `
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly U. d! m5 B0 d2 A) w
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it. ~7 L; v* V- H
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
* N _$ W5 I9 }$ }- Q) n1253424 SCM SCHGEN Export Schematics Crashes System Architect
& w: _$ t H9 d1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled: M, }' L7 J: q9 I, b5 j/ i6 f
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
; W) @' |" o) R1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router# p4 W! F% P4 [
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error) L4 f) S: e" j! {. K
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.7 s" y. n% E0 [$ B8 W6 _' o2 g
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation/ ?- h, r5 j0 A+ Z( c: C6 Z
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects7 U) O) z* F4 X4 |2 |# _
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
$ ]* l: Y$ _9 Y) [- p# i1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided. O1 v% m5 c0 U9 T N
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
# k2 w2 I1 B4 N; t- j; d2 r- L" _1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
3 ? m: m, ]- _( G1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
' ^- `. f/ p& e) N, b1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library7 w; r/ u( z n y6 P. B9 W* f, b
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long0 q, f% l7 V+ f" V* N9 f
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash t9 t0 F4 t# S, c! m
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time4 }5 N9 ]' \9 e" {" e
1258029 APD WIREBOND The bondwire lost after import the wire information
m- `' D9 V; @0 b8 g- I5 @1 x, s1258979 APD NC NC Drill: There is difference of number of drills.
3 V, j9 S, X! ]8 O1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement8 v8 ]8 i, d9 b3 q8 p& Y1 F% p
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
1 n* I2 z) @8 Y" j9 b& A1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer" t8 y* ^. `5 M) M7 `+ D! l
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
: w& T" _) o" G# G( y. a1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
& m7 u6 V" N5 o4 D: {6 g2 t1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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