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27号补丁修复的BUG较多！
, a8 e# r& @( y4 {! {4 H- g9 b百度网盘下载链接http://pan.baidu.com/s/1mgwSsPy/ r! R; b- U1 h' K; c E: x7 W7 U
- U. q1 t) R& J- UDATE: 04-25-2014 HOTFIX VERSION: 027
3 i- w7 V& k* @' t" o) H) f/ v===================================================================================================================================$ F$ o% E7 G* @" f% M' T$ R8 ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE
3 A: @2 D0 B' _" I1 U===================================================================================================================================
2 ~4 `' u ]1 ?; c+ Q308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
2 P: g& T+ j( k5 y, r481674 allegro_EDITOR pads_IN No board file saved from pads_in2 \/ t! s. w, E+ |7 \
982929 allegro_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.6 N( W3 r4 S+ h: J4 w+ `
1012783 FSP OTHER Need Undo Command in FSP1 c1 c) p& j S; L' _6 O7 E g0 ?+ c
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.. y, f: Y0 g) E' i" R+ T& |
1072673 pcb_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved2 C9 g% C# u1 o$ T! X) T% h% e. V; N
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.! Q- U) Z# ]0 l
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups6 y% y, g. Y1 V5 \' u! S
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
/ _8 c: i( C. d4 F0 k7 y; q1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command
) T' {( [; y' Y* R; D2 X1 t! Q$ j1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
% h$ J- h1 t2 F( K, ?7 l1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present: H/ j5 N w1 o' c3 {/ Y
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
?9 q5 c: Z! ~' {! F! s1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings0 R4 Y t& d0 \* f7 T
1185575 SIP_layout DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
0 c8 q- N5 E# \& t% ]6 `/ P1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
: T& j$ v) Z: Q3 p7 ~/ o1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
" B* E# W1 Q+ e1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates8 b2 `1 D4 k% l) g, t
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
+ \9 f% p0 E& d# P1208478 PSPICE PROBE Attached project gives overflow error with marching ON.5 [$ ^! g' e8 B: \0 ^. N/ V; U
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol/ I3 l) p3 P8 B& T/ `
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed; v8 S; h$ L+ a) `/ A
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape0 r9 Y1 ?9 O1 \5 G5 z/ g' u- B
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers; O' [ a( u: p
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?( H5 S- k9 {- R, `
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed." R0 I: ?! L( v) A
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values/ I* u; Y- N* |. n# D6 b
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging- [6 J: w0 V5 U
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
$ |% M: O, O0 o! X1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added! \1 G$ i3 g2 J" w0 r! ~; T
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness." g- |3 f# S$ X( x* q
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
% `9 ]/ a0 l3 s' B4 Z) I8 s( o1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux. B) g. |; }# N" a- o$ k$ g
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
: g0 I1 Q4 W: d0 e5 g7 J& c1221182 ADW TDA Team Design with SAMBA: f6 p0 M$ n. T4 s3 N. o
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
% w/ ~2 q) }% V9 N) b( m6 W3 p- n3 h1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
; Z- x$ k- {; o4 O9 I1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
s2 p: ^: j) g3 i8 ]1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
, ]; S/ l0 W" y1 y1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
& x, _9 V3 v+ r, z) g0 }( d! v1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
! k$ r% u h, e: n6 ^1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor; I8 z3 N o: n `8 D
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.0 h D: P& X; h$ b8 X
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path6 U) I; Z3 V- a
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin" N% a! w" A6 ?: ]5 y
1225494 CAPTURE DRC Different DRC results for Entire design and selection+ r- C2 A7 v1 F9 {9 T- q' b
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property/ I( O- u( p3 ~* z
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet3 C1 S! @- s/ [9 X7 m2 v0 W
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet; E$ g) ]. ?3 i6 [/ D4 P
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal( r# r/ `4 p# Z4 @9 J
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
) _' Q$ `8 p7 `: b4 r# G2 T1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors4 k, P! Y/ k+ p3 p9 y) w
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8' w$ N5 o4 W! a8 }
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration% N) j0 ?# w. J4 ^
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part" S$ F! M. A) g! S! Z: h3 v
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
) d7 d! J. I2 K$ `* }4 W1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins, X7 c8 i3 N( s8 H4 L N
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
* Y0 G% U. o6 {+ N: O' M1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.3 k7 L$ W* Z3 c; x8 H* D
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.3 z0 Q4 Y' e. S4 t0 O
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).8 G5 S# e1 a- z* g! g `: y/ ~
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
: D' j# j- i5 \, X& G% A9 R1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined1 ~: R% g; F+ |+ b3 B) \1 a8 e% s
1230432 CONCEPT_HDL CORE No Description information in BOM
6 h# v }) r! n1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes3 d5 T/ ^5 N* p$ H' O9 u
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files# ^' | a$ ]* n9 O8 N6 Y# e
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
3 q0 Q+ B6 A1 y/ C1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets# x, z$ H$ W' r# M0 J/ K6 B2 ~
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
2 X. M4 t- c( w: G0 g8 G1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode9 D4 @ Y1 f/ q4 M" z% D c
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
1 R5 P" y) f+ D3 q$ G2 P( e9 I k1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode
' y( U H7 Z& }1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files: |3 S# g: p# j4 o. c v% M
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy. \$ ^! ] t+ U* [/ u) {$ W
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
8 }5 f9 f/ o" \! v9 x" M" s1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect1 t8 J# M2 ?- W2 Z5 a
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
# c3 @7 K% f& ]/ A1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
2 d5 m2 h3 P2 ]7 B1236161 CONCEPT_HDL CORE Import Design shows the current project pages% D3 `6 |. _( m$ V& T
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
( f4 c3 n4 a' s) V1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
0 c* K7 P7 e0 }* f1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
" f/ U) {: w! E w8 [0 X! p1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape2 d5 w# g \: W' O0 K. r+ U
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming2 u7 \: X3 y8 y/ R
1236781 F2B PACKAGERXL Export Physical produces empty files9 K7 b/ e1 j0 e0 b
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
5 p) M5 v1 B3 B( I; e" M ^) T1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command3 y) s( J6 p9 b [+ m2 t
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition* s, `; [/ a1 C) n7 E! i
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.4 Y! I) O c# N- E9 n% a, a
1238852 CAPTURE GENERAL signal list not updated for buses
$ V3 X* z! Q/ A: y1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
{5 N) U' A% o0 ?8 G8 g& L# z* W( g1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.1 i/ S/ {7 t) i5 Y
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
$ ]6 a4 }( b' _! x5 p3 p( j1239763 PSPICE PROBE Cannot modify text label if right y axis is active
! [* _' |" b) {1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images4 r% s4 k1 c+ U- [! u9 j
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
) ^5 m& h9 n2 F5 H" D3 W1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing1 `/ M; h$ g) @: W! n1 c
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
) g9 N1 {5 I- b/ y# Z, T1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable+ \' o) N5 e- \3 U O; A
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy6 z. y. e& E4 m7 b- O% `
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms: A0 A. I) W5 N& p: p+ i$ K2 ]
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working0 ]) q- e* r2 `8 { t* H, L
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.& U1 {$ w/ O$ `2 R( b9 y
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
7 z( X) ^9 a. Z+ M. r1 h0 D1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning+ k2 ?( {) d9 q
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
9 W2 e) E+ P5 g1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
# ?5 i' q- a! W3 y$ n1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
4 `. x$ s8 @: e1243609 CONCEPT_HDL CORE autoprop for occurrence properties3 L1 m- a! |; K v6 l
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
, O0 B9 r/ y& e. h8 V6 W# `! _# J) R5 m1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed., q8 g# l3 t8 F7 H3 O6 M; }3 X5 \. M
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
6 S& u/ }$ |2 L. t6 @1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder- Q+ ^8 N; ^* H2 Y5 |( t
1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
+ U2 d8 h- ~3 O3 |1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design2 D' z& A: v' A$ b! V% V
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?- @+ ~: c2 q) I' x& Q/ Z+ L$ t) l
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
" z( t' I4 U# p1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
+ V1 }$ R, I: M$ ~' p5 Z% \1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
3 D# O% ^+ @9 Y1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
$ ` T9 K L" k. ]; ~# Y1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL3 c) z* r. ]( V. W/ G$ A
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
5 x K! {( @+ @7 D1247462 CONCEPT_HDL CORE Text issue while moving with bounding box3 }% S6 }% A2 p N
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered$ [3 n1 j$ m$ t
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
+ k8 _; T8 ]" P1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
/ I$ l& `" W% f4 a8 T2 ~) P1 @; Z1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.+ a4 _0 S3 D Y$ i$ M p
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint, x" l: S B% k8 {
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
( q2 T- R+ m+ |$ e1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
4 @( H' F5 m9 P$ u) U5 [" R1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies* D1 m- R, R5 G) y
1253424 SCM SCHGEN Export Schematics Crashes System Architect
% J2 k+ u2 n( X4 ]. ^2 C3 P* C1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
1 \/ d a. c& A4 g' V1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing: t, { O- ~) A
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router( \! |# {" x5 Q4 b
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error, k7 H O1 ?9 v
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
+ A" \; \! ?9 M$ g$ e. Y3 N1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation+ o$ D9 X: t; B, y& A: a8 v
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects
& x' a: h- I+ C6 z; F6 P1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
) w7 J% u; M3 s; H+ S- [) E2 b1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
4 y& {' n0 F! b p. d: K- W1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE" j% v" r. N8 [; w4 [, X! W
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
! e) Z. Q2 `/ ~" r1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
! F9 V, M& D: E1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
# T. I* y, H! N1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
- I% Q; U, m. } l |; _3 x1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
5 ~: k9 \* J8 ]7 M9 ]4 \8 X1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time5 t8 }8 J6 k' a% I7 }7 G
1258029 APD WIREBOND The bondwire lost after import the wire information
, l5 O! e/ M+ Q" R) P1 j3 v1258979 APD NC NC Drill: There is difference of number of drills./ X" W5 X- U% \
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement5 B" @! M* S7 K' _7 y
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.' w6 v7 s; F7 J( D7 x# m5 M
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
& Y1 a. ^7 u- I: P1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
1 C2 M! C) Q* S- Y1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
. k7 H$ n z4 D) V5 V8 e1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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