SPB_16.6 27号补丁下载链接--Hotfix_SPB16.60.027_wint_1of1.exe

cesc

27号补丁修复的BUG较多！
. x6 x% Y" n7 }& A' ?' l' W6 R; Y- R百度网盘下载链接http://pan.baidu.com/s/1mgwSsPy
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DATE: 04-25-2014   HOTFIX VERSION: 027
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
. G. w4 S$ M# f: j9 Z& Z===================================================================================================================================
: ]+ t9 s5 q/ v308701  CONSTRAINT_MGR OTHER            Needs to delete user defined schedule in CM
481674  allegro_EDITOR pads_IN          No board file saved from pads_in
- V: Z7 ~8 P2 l. U, o/ v" b, }, d982929  allegro_EDITOR EDIT_ETCH        can't route on NC pin and other that are not pin.
1012783 FSP            OTHER            Need Undo Command in FSP
6 s* D' l+ g) R1 @1017381 ALLEGRO_EDITOR DRC_CONSTR       Need Dynamic Phase to be able to measure back to the Drive Pins.
1072673 pcb_LIBRARIAN  GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
3 M- q% ]' _) \% `) i5 O" Z! L1073231 CONCEPT_HDL    CORE             Copy-paste of signal names goes off-grid in Windows mode.
3 L+ D5 S9 n2 [) @* a  e1105371 CONCEPT_HDL    INTERFACE_DESIGN Strange behavior when shorting two Net groups
: [5 Q' j+ {. N' ]( X' }) c" [1116498 CIS            LINK_DATABASE_PA link database with modified part results in Capture crash
; g4 z' a1 v7 F4 I1118632 ALLEGRO_EDITOR GRAPHICS         Text display refresh issue while in Edit > text command
1155821 SIG_INTEGRITY  LIBRARY          Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode
1 k! w, Q$ Y- }" |0 e, _/ _% c, r1157372 ALLEGRO_EDITOR DRC_CONSTR       Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
1171951 ALLEGRO_EDITOR CREATE_SYM       Jumper has a limited of count when it add to list.
5 D1 l* z4 J: d4 U2 e" t: q; I1180871 CAPTURE        LIBRARY_EDITOR   Copied parts don't retain pin name and pin number settings
1185575 SIP_layout     DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
1185772 PCB_LIBRARIAN  CORE             VALID_PACK_TYPE warning when cell was opened in PDV
1 V) ]! n9 i. d. l6 Q1192377 CAPTURE        SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
1202654 ALLEGRO_EDITOR GRAPHICS         Zoom using mouse wheel shall maintain the center co-ordinates
1208031 ALLEGRO_EDITOR INTERACTIV       Snap to Pin for via during Copy command do not snap to connect point everytime
1208478 PSPICE         PROBE            Attached project gives overflow error with marching ON.
* \* r% X/ p( A5 w" R" D1210015 CONCEPT_HDL    CORE             The value of $PN should be not turned on spin or rotate symbol
, }$ U- u9 Q0 Q' Q) p  A1210425 CONCEPT_HDL    CORE             When moving a circuit tool reports that connectivity has changed
% ^* k, W3 n; x+ y: ?2 c/ d6 E1215858 ALLEGRO_EDITOR SHAPE            Force update does not void cline with the shape
1215906 ALLEGRO_EDITOR SHAPE            Dynamic shape fill smooth failed when copying to other layers
; u3 A- G1 z: y* ?7 x# M  m1216358 CONCEPT_HDL    CORE             Can we improve our export BOM function to check if user did export physical function before exporting BOM?
8 ^3 e& }' o4 t! M7 x( P1217364 CONCEPT_HDL    OTHER            Netlist reports fail because error: GScald failed.
1217529 CONCEPT_HDL    CORE             ADW checks do not catch single quotes in PTF values
1217556 F2B            PACKAGERXL       signal name change not sent to Allegro after packaging
/ c+ z, e" N! ]1 }- ^1219283 ALLEGRO_EDITOR DRC_CONSTR       Show constraint is inconsistent when displaying region information
1220078 F2B            PACKAGERXL       Export Physical crashes when ALL the part pins are added
' g8 G6 k  }6 b; C1220393 CONSTRAINT_MGR CONCEPT_HDL      HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
8 y9 l9 G; m- E. ]( c% {1220540 ALLEGRO_EDITOR GRAPHICS         Need an option to see the pads inside the internal plane shapes
1220936 CONCEPT_HDL    CORE             About crash by vpadd/vpdelete command on Linux
+ ?) e$ Q% L5 ?7 w. z1221059 ALLEGRO_EDITOR DRC_CONSTR       Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
8 K+ d  H; g1 T! t: Q  u1221182 ADW            TDA              Team Design with SAMBA
9 G5 U, [" p9 P* q& a* H, w1222442 CONSTRAINT_MGR UI_FORMS         Duplicate pin pairs appear in DiffPair
1223175 CONCEPT_HDL    CONSTRAINT_MGR   Schematic crashes when opened
1223533 ALLEGRO_EDITOR GRAPHICS         Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
$ Y5 p6 i) X  u6 W9 `1 p1223680 CONSTRAINT_MGR ECS_APPLY        Improve ECSet mapping by allowing user to address ambiguity of Parts
7 l5 f# j9 i& z* y* G9 d1224156 SIG_INTEGRITY  SIGWAVE          Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
; c! B4 O  m" |. o: [( h1224417 ALLEGRO_EDITOR PLOTTING         Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
1224704 F2B            DESIGNVARI       There is no lock for the variant.dat file - multiple users can open the editor
1224968 ALLEGRO_EDITOR INTERACTIV       Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
5 _$ c1 y" d3 Y8 j+ }$ h1224982 CONCEPT_HDL    PDF              commandline publishpdf does not work when there are spaces in the path
3 x  g: G6 o7 o) U% O1225114 CAPTURE        GENERAL          H-pins added after netgroup pin get color as of netgroup pin
8 a0 {, L; U' g& s1225494 CAPTURE        DRC              Different DRC results for Entire design and selection
1226153 ALLEGRO_EDITOR INTERFACES       Export STEP should include PART_NUMBER property
& Y, N9 n$ r. l4 D0 I) n6 R) l1226235 ALLEGRO_EDITOR EDIT_ETCH        Enhancement to include Pin_delay of descrete forming Xnet
1226372 CAPTURE        GENERATE_PART    ENH: Functionality to add pin spacing in New Part From Spreadsheet
1226477 CONCEPT_HDL    CORE             DE HDL縮 `Allowed Global Shorts?  function is inconvenient for Global Signal
2 Z2 p; j! {9 S8 e$ [& u. ?# a1226813 SIP_LAYOUT     LEFDEF_IF        ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
( X5 m) y8 r; ]8 L3 a1227453 ALLEGRO_EDITOR SHAPE            Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
$ r( i0 m) _: T* O# W5 ~" P0 F' P) Y1227461 ALLEGRO_EDITOR SHAPE            Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
1227469 CIS            DBC_CFG_WIZARD   Oracle Views not visible on Step2 of CIS Configuration
1227780 CAPTURE        ANNOTATE         Inconsistent behaviour when annotating heterogeneous part
' ~; G+ W' O. B  _1227831 CONCEPT_HDL    CORE             Pin text and H-block name in upper case
; h" v# k/ b" Y0 }/ ]8 {+ v1227954 CONCEPT_HDL    OTHER            supress check for global signals when wires are unconnected to pins
1228190 ALLEGRO_EDITOR OTHER            Unable to close the 'usage' window during license selection
/ Y& `( {: h. _7 d1228899 CONSTRAINT_MGR INTERACTIV       Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
8 D. h5 }5 b$ R% g! i" _1228934 ALLEGRO_EDITOR EDIT_ETCH        The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
1229316 ALLEGRO_EDITOR EDIT_ETCH        When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
1229545 CONSTRAINT_MGR OTHER            Allegro indicate bundle scheduled nets in CM
; d# b5 _6 ~- t$ D1230056 ALLEGRO_EDITOR GRAPHICS         Bug: 3D View of Mechanical Symbol with the drill hole defined
1230432 CONCEPT_HDL    CORE             No Description information in BOM
; T5 j5 J7 d$ \1 L1231148 F2B            DESIGNVARI       The variant.dat file is not updated with library PTF changes
: j0 d+ Q7 B' g& {( I1231625 F2B            DESIGNSYNC       VDD at command line needs to support sch2sch and test variable to write out report files
6 B0 o4 J7 C" ~1231697 CONCEPT_HDL    CORE             If any locked files exist force a pop-up dialog restricting certain commands
1231767 CONCEPT_HDL    OTHER            Unable to find under the search options single bit vector nets
) H# w' o9 b0 H1 T1231961 ALLEGRO_EDITOR SHAPE            Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
* D2 q' {' X. A- C' M1232100 CONCEPT_HDL    SKILL            Unable to execute the SKILL commands in viewer mode
8 @  D. \/ n8 r% w/ t1232336 CONSTRAINT_MGR CONCEPT_HDL      cmFeedback takes 5hrs to complete during Import Physical
1232710 F2B            DESIGNVARI       Dehdl crash while moving component in variant viewer mode
& l0 Q4 ?% y) I/ r, w) i- }1233894 F2B            PACKAGERXL       The page data is missing in the pst* and PCB files
+ O9 _$ A* ~" y) G- [1235785 CONCEPT_HDL    CREFER           cref_from_list custom text is not subsitituted in complex hierarchy
# G5 l0 l* I1 X2 P/ c1235928 CAPTURE        SCHEMATIC_EDITOR OleObject modifications not saved
1236065 CAPTURE        PART_EDITOR      Mirrored part after being edited get pin name locations incorrect
( v% f& D5 d9 j7 K2 P) Q1236071 ALLEGRO_EDITOR SHAPE            Airgap for Octagonal Pads ignores DRC Value when Thermal set
8 U: f, [# T9 n  B3 u1236072 CONCEPT_HDL    CORE             Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
/ [) k2 a; z( [, i1236161 CONCEPT_HDL    CORE             Import Design shows the current project pages
1236432 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translate via and shape in some instances.
1236557 CONCEPT_HDL    PDF              Running Publish PDF on command line in linux doesn't output progress until completion
1236589 CONCEPT_HDL    PDF              Enhancement license failure error should appear in pdfpuplisher  log file
" a) V, g+ z1 [+ s  N& B1236644 ALLEGRO_EDITOR EDIT_ETCH        create fanout deletes shape
1236689 ALLEGRO_EDITOR GRAPHICS         Graphics displays extraneous lines when panning or zooming
1236781 F2B            PACKAGERXL       Export Physical produces empty files
' J, W. G) T9 F/ E: u1237331 PSPICE         ENVIRONMENT      pspice.exe <cir file name> - hangs when run
5 R; ]* l$ Q, D1237400 CIS            EXPLORER         Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
8 ^4 r( X7 z" a1237437 CONCEPT_HDL    CONSTRAINT_MGR   CM Crash when saving after restore from definition
& u" S. l, Q! o; D8 K) M1237862 CONSTRAINT_MGR OTHER            A way to remove the RAVEL markers from the Constraint Manager.
1238852 CAPTURE        GENERAL          signal list not updated for buses
1238856 FSP            DE-HDL_SCHEMATIC FSP schematic generation crashes
; Z7 w- W) L9 P, ^6 S1 k1239079 ALLEGRO_EDITOR INTERACTIV       The 16.6 Padstack > Replace function leaves old padstack.
1239706 CONSTRAINT_MGR ANALYSIS         The reflection result on a differential signal in the CM when Measurement location is DIE
5 I4 {7 N7 c5 W1239763 PSPICE         PROBE            Cannot modify text label if right y axis is active
* W  |/ n7 `9 d6 P& h: k$ W8 Q1240276 ALLEGRO_EDITOR GRAPHICS         Printing to PDF from SigXp is giving unreadable images
7 u8 P" M9 J; `4 C/ D. ~1240356 CAPTURE        IMPORT/EXPORT    Can縯 import SDT schematic to Capture.
1240502 F2B            PACKAGERXL       Corrupt cfg_package does not stop PackagerXL from completing
! R5 V+ e1 i! n( j: P+ `8 S0 g+ ?1240607 ALLEGRO_EDITOR OTHER            Footprint of screw hole got shift in DXF file
1240670 ALLEGRO_EDITOR PLACEMENT        Select multiple parts and Rotate makes them immovable
% K5 P& ~5 n/ I5 x1240773 CAPTURE        DRC              DRC check reports error for duplicate NetGroup Reference in complex hierarchy
1240845 SIG_EXPLORER   EXTRACTTOP       Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
1241634 ALLEGRO_EDITOR OTHER            Netshort for pad-pad connect not working
( F4 `; W- ]0 e" @: C1241776 CONCEPT_HDL    CORE             In hierarchal design not all pages are getting printed.
# M2 U6 ~; L6 A1 l! G7 b8 `1241788 CONSTRAINT_MGR CONCEPT_HDL      Issues with changing focus in Constraint manager using keys on keyboard
; t7 x+ ?3 D0 G+ d/ C1242683 ALLEGRO_EDITOR INTERACTIV       Color View Save replaces file without warning
1242818 ALLEGRO_EDITOR PLACEMENT        Placement edit mirror option places component on wrong side
1242847 ALLEGRO_EDITOR GRAPHICS         Need an option to suppress Via Holes in 3D Viewer
1242923 ADW            COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
1243609 CONCEPT_HDL    CORE             autoprop for occurrence properties
1243682 F2B            DESIGNVARI       after undocking variant icon cannot be redocked back to GUI
3 P/ r% r9 u/ ?- e$ A5 |1243686 ALLEGRO_EDITOR GRAPHICS         Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
1243715 CAPTURE        PART_EDITOR      Pin name positioning get changed after rotating or mirroring
/ e$ M$ W8 a+ L% y/ S2 l1244945 CONCEPT_HDL    PDF              PDF Publisher does not include image when file is not located in the root folder
% F8 L# O8 j) s1245568 CONCEPT_HDL    CORE             Dual unselect needed for wires attached to other net/source and property is not deselected when component is
0 L2 C- E( ~! K/ U% e4 v0 x1245819 F2B            PACKAGERXL       wrong injected properties information passed during packaging of the design
7 x" ]; M- h! V. }$ I, k1245916 SCM            CONCEPT_IMPORT   Where does the folder location reside for DEHDL imported blocks?
4 Z5 ], k9 |; x- ~/ L6 l1246347 CONSTRAINT_MGR CONCEPT_HDL      DEHDL crash if environment variable path has trailing backslash character
1 O8 _; I2 d5 |! Y1246896 ALLEGRO_EDITOR DFA              DFA_UPDATE on Linux reports err message if the path has Upper case characters
) D/ H8 Y6 s! i- U( v% d2 c2 B1247019 SIP_LAYOUT     DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
7 L3 t" {/ U: ]( i+ L1247037 CAPTURE        LIBRARY_EDITOR   Copy & Paste of library parts resets pin name and number
1247089 CONCEPT_HDL    CORE             Group Align or Distribute > Left/Center/Right crashes DEHDL
1247163 CONCEPT_HDL    PDF              Physical Net Names in PDF not maintained
1247462 CONCEPT_HDL    CORE             Text issue while moving with bounding box
4 M7 f+ d" Y; f& i' q1247464 ALLEGRO_EDITOR UI_FORMS         When using the define B/B via UI the end layer dropdown arrow is partially covered
1 ^+ X3 K2 K( ]1249063 CONCEPT_HDL    CONSTRAINT_MGR   CM and SigXP doesn縯 respect PACK_IGNORE at components
" {& y4 D& @& h* P. H, S: ^- k0 r1250270 CONCEPT_HDL    CORE             Part Manager Update places wrong parts
0 `$ o8 ?; N6 }+ r9 S1251206 ALLEGRO_EDITOR ARTWORK          Aperture command cannot create appropriate aperture automatically from design.
1251356 ALLEGRO_EDITOR INTERFACES       Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
1251845 ALLEGRO_EDITOR EXTRACT          Crosshatch arcs do not extract correctly
0 C6 q- g! ?# ^, ]- R9 z1 f1252143 APD            OTHER            When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
$ ]5 N, Q( B. I9 G3 k1 N1252737 SIP_LAYOUT     OTHER            SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
; Z1 v/ P# e% y+ \9 a, ?" _6 G2 D1253424 SCM            SCHGEN           Export Schematics Crashes System Architect
0 {( ^; m/ e0 q2 C/ J- n0 y1253508 ALLEGRO_EDITOR INTERFACES       Bug - Export IPC2581 exports Crosshatch shapes as filled
5 y) u% A) {9 T1253554 SIP_LAYOUT     OTHER            SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
1254578 SPIF           OTHER            Specctra crash with Error -1073741819 for Auto router
2 C1 d% T  I) U& q/ ?1254637 ALLEGRO_EDITOR DRC_TIMING_CHK   adding nets to a net group causes constraint assignment error
9 [: s/ b3 q7 _: j: s1254676 GRE            IFP_INTERACTIVE  Rake Lines disappear when Auto-Interactive Breakout is enabled.
) T: s7 v, \  ~- h1255067 SIG_INTEGRITY  REPORTS          Allegro hangs on Net Parasitc Report generation
1255267 ALLEGRO_EDITOR SKILL            axlDBGetPropDictEntry does not return a list of all objects
1255383 SIP_LAYOUT     IC_IO_EDITING    cant move bumps or driver in app mode
8 |3 a  W( R! r& S1255703 ALLEGRO_EDITOR SKILL            axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
3 ^4 C6 h4 O. Q' j& K1255759 ALLEGRO_EDITOR INTERFACES       Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
1256457 CONCEPT_HDL    CONSTRAINT_MGR   Extracting a XNet from CM crashes the tool
1256597 GRE            CORE             Allegro GRE crashes while running Plan Spatial, on a particular design
1256650 ASI_PI         GUI              PFE - Cannot generate model file error when using company decap library
$ G7 U+ ?/ M. u( j1256837 SIP_LAYOUT     DIE_EDITOR       Open and close of die editor takes too long
1257732 CONSTRAINT_MGR OTHER            Bug - Export Analysis Results in CM makes Allegro crash
% g/ V% r; h, a' }1 w9 o0 a1257755 ALLEGRO_EDITOR OTHER            Editing time in Display > Status seems to be logging wrong time
1258029 APD            WIREBOND         The bondwire lost after import the wire information
1258979 APD            NC               NC Drill: There is difference of number of drills.
6 ^0 {) C% ^7 |1259484 SIP_LAYOUT     OTHER            SiP - calc min airgap calculate minimum airgap beta feature improvement
& O( _* k5 {) I2 }( }1259677 CONCEPT_HDL    CORE             hier_write -forcereset cause component prop change.
& [2 ?; p; Y9 V+ ?1 n  L' P5 e1259913 ALLEGRO_EDITOR UI_FORMS         Unable to save setting of "use secondary step models in 3D viewer"
1261758 ALLEGRO_EDITOR EDIT_ETCH        Auto Interactive Delay tune (AiDT) is deleting clines
" w* h: p6 [! S' ^/ N- `9 O* r' F1262543 ALLEGRO_EDITOR MANUFACT         merge shape results in moved void
& r6 {" C. E' A' Y4 K4 q0 P1264767 ALLEGRO_EDITOR DRC_TIMING_CHK   XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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