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27号补丁修复的BUG较多！
( `" j5 J! v% W5 X Y百度网盘下载链接http://pan.baidu.com/s/1mgwSsPy
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' c+ s% _% g1 u2 y6 mDATE: 04-25-2014 HOTFIX VERSION: 027
3 |0 p8 w6 r" P& p===================================================================================================================================! O# S3 M* S+ A7 S& L! O1 D6 `
CCRID PRODUCT PRODUCTLEVEL2 TITLE h' k0 Y! ~/ [3 F# V
===================================================================================================================================- z! r0 ` t; R1 N; j
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM- a6 ^- V q+ ?- s
481674 allegro_EDITOR pads_IN No board file saved from pads_in, n7 |4 ^9 J i: n! Q
982929 allegro_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
@+ o& J3 \5 |) Q1012783 FSP OTHER Need Undo Command in FSP
m& V; H8 i( b( S$ I1 X- j1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.5 J; V5 n/ K, N( U
1072673 pcb_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved2 V# |5 i. S- q! `1 x5 E
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.8 b5 n; ~, C: E: z5 U& H
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
$ N5 O" _1 j4 K1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash! w3 ` T8 p& }8 X' K9 U
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command1 H) s# Z2 [, W* S! \0 G4 r
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode4 Q9 P- l' C! b7 V6 \) s5 a
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present# t* D: l4 N& d* M7 ?3 [6 ~7 Q
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
+ ^2 D; |4 V1 _0 @7 x1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings0 E+ k" H [ s) V8 p
1185575 SIP_layout DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
0 w7 h' W$ B- s4 w% F1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
# S! G* K& W% u3 T: b4 c/ f1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.# x) I& o2 ~% }5 T
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
1 T+ O7 P6 T. |2 _2 e1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
' ?9 _6 y+ g1 T, z4 r1208478 PSPICE PROBE Attached project gives overflow error with marching ON./ M6 R; g: q5 |
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol; E3 o* X. Y0 G, _% e: u( l$ Q
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
1 i/ z p% a; a9 w3 [: X3 S( s1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape- g; A0 F- B8 _+ }1 r" C5 e4 h$ Z7 C
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
) A$ j1 D5 {& k) o) i* w" E! L$ z1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
7 d. R; ^0 N, E: v q* o1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.; o9 p" b. n" @. u/ s9 p5 t: F
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
0 Z" {$ Q1 F4 K% N1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging2 \. l9 m* k1 E
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information' H$ o7 p, ]) t" o( H' `! \+ B
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added6 f7 t' t7 l/ `! y, G9 U
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.5 b0 n% O8 z W5 n/ X; W
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes5 ]/ O, a0 o( z( h r/ w/ L
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux0 A9 S/ ?3 f- v7 L) m* T& n
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.7 S* e, u5 S' z; y/ v
1221182 ADW TDA Team Design with SAMBA
% e; E# S4 X- M" A: u1 N1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
# l6 h9 z% ~. q: _/ k- [1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened3 R# A( O8 K, Q2 G1 [/ k
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?" k4 j) v$ l; _/ R5 U) w
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
. E7 E9 t1 q, o/ s8 w' K/ E1 W1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
8 E6 _+ N0 k) h/ S1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.; h) I, q4 G" _9 ^* K
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor& o& w. S+ y" R2 h/ K
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.0 n; V; C$ @) s" M4 n1 n
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
1 V: [ ?2 n; k {, R1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
& g$ }; K! X8 ]0 ^2 e* O1225494 CAPTURE DRC Different DRC results for Entire design and selection! e5 s) i/ j- C. d
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
6 P4 J7 g& h3 ]6 L8 u9 E1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet7 G: F3 V# f6 t( o8 p
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet( V1 f* r/ M0 B7 K, a
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
1 n; w( Q4 b( G9 e5 H# s1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file! m! Z8 h& y4 f5 X: \- _
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
! f$ {' v# _+ e7 j3 [. Q. e' w1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
4 b, V+ H! Q# _6 }3 B' K+ D1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration' x( k2 A/ ?4 B- M. @: q9 f
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
7 |' H9 `$ V, I0 T0 h! J1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
; V. Y% H1 e9 }5 j1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins, W" a2 o, \# {) x8 l
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
* {* u" {! z ^ B7 l W1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.& O! t. X( ^/ ^; B/ d: z1 l
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility." T" F$ }3 P3 ~# A
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
; m2 q* N- A/ |1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
# S/ y; W; O( k l6 Y3 x1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined) V# C j4 K7 C4 ]+ i8 J
1230432 CONCEPT_HDL CORE No Description information in BOM
, ?. ?: q0 Z# U6 X8 s1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes v$ c: G: Q# F4 Q; H
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files% F! u% o I- `" E/ l
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands! s, j1 ]$ E# ~* [
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets. Y1 I, Z' [' D0 G8 O
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
5 b9 }4 c, G$ n% a' L1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode; H2 f) Z7 p7 T$ s) u6 u
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
1 S% L' e* z' a1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode \8 L4 ]7 Z# ~1 F- `" x. }$ Y4 |4 l! u9 D
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
1 Q' f4 O2 x! c% v* w1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
6 T+ a6 Q# g" V, c1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
3 }+ M0 O' l& a: Q9 T3 J, {" Q1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
( l8 \8 z" K+ G: q3 m1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
0 R7 `+ i: _, ` l+ I6 E1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
2 g8 Z& S" i' ~$ U2 G ^1236161 CONCEPT_HDL CORE Import Design shows the current project pages( W( V2 N* K8 z' n M: W. K4 N
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
: P8 O$ d+ G) W6 B' P1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion7 U$ y/ h3 E) r+ |) U1 W
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file( l7 u9 o6 E, }7 n- B {- f
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape' a% X& e) L. W; c( r
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming2 O/ \8 R* k# b
1236781 F2B PACKAGERXL Export Physical produces empty files; |3 ]6 [; ]0 z, A! ?
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
' J9 b2 d( C4 @. R# J. j1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
' I4 ^: X: }: l3 Q8 g1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition% Y7 k! }$ {4 I5 N- M+ q
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
# f. V6 @. x5 N& S1238852 CAPTURE GENERAL signal list not updated for buses
1 M4 }! w7 u0 z) U& c. o1 q1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes+ q$ W3 b' x1 B* _% F: t
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
7 J0 i/ p! }1 X# Y5 m1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE1 B9 S% b& r/ R# |0 S/ b
1239763 PSPICE PROBE Cannot modify text label if right y axis is active. H. J; W6 H2 N7 Q% u; e
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
: k6 v, w8 B j$ Z, g1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.2 d; J8 ?6 H9 l+ {3 F; ~2 j' P
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing& M: J- }+ f8 _. k7 x3 T* m
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
9 c4 O7 ~3 s) [6 _, z! m+ t1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
9 T3 H% @! R9 R, _1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy- R2 B+ ]9 h0 V6 a
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms! ^( k# u7 b9 W, t+ H
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working: }: i" k5 B8 G$ V4 X2 F$ z
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
2 a$ S4 ]2 R& w! S' b8 Z1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
b9 o) p+ d# K1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning A' o9 t) q V7 P2 b
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side7 F) O5 B2 I# ]: L" ^3 k6 i
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
: \4 |, r" _( x9 y# W5 w1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results Z/ t6 u" W) z% a( R0 F H2 m. ?
1243609 CONCEPT_HDL CORE autoprop for occurrence properties
# q6 I$ f: s9 R: X6 t, o1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI7 [6 c& d9 R- b( _) Q7 x% C. F9 Y
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
, S! V! j8 v& V9 f1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring7 N; N' p* H6 M! c/ ^7 V
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
3 g7 a0 X. L8 l5 c) Y0 {2 Q/ g1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
9 @; F# b( W- t7 p" B8 w7 C- H1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
0 j) o/ N: v) u: N+ f+ X: A! _+ K1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?( `7 N/ t( s' X9 }, ]
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
. {+ g: L( x% b" C6 A* [1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
8 A+ C. w' @0 s2 Q* r( o0 z1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown; [" q- O7 I( ?5 F \
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number+ Z& C( M4 g9 p' i2 @$ j5 r2 W7 W' P/ c
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
0 n1 i+ A6 O$ i1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained: u7 m% r) @. E7 Q$ V( m9 I
1247462 CONCEPT_HDL CORE Text issue while moving with bounding box" Z$ _0 Z6 E6 y! q6 w/ k
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
8 E/ G# M' s% C* R$ T3 `1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
/ z3 |2 ?- z* _3 C1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts+ \. a; H/ ]5 T) v
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
9 x4 f: I$ I# K0 Z1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
l) f5 A+ b& H- ^6 a+ Z1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
7 o3 ^# [$ Z9 P1 @4 e; ~: _1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.9 W; ?) O- v6 q. i5 o/ a
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies: ~& f" \. M7 t9 C8 I
1253424 SCM SCHGEN Export Schematics Crashes System Architect
6 R$ b3 d9 ^( r" D: {1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled
3 T2 K8 j( l9 h( [ ?1 h% O j2 Y1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
. J5 z6 u C1 e1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
+ |' Z# ~6 P+ f' D$ m1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error/ [6 G9 t& ?: ^) i' f
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.8 q/ Z! s1 T* F0 |
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation. R$ ?4 j0 i) j9 R* V
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects
% W q* z' j. j5 F1 p1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode+ ]+ @$ I! Y" Q o. S/ E
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided8 W# v' e2 W3 Y3 z( T6 L4 D3 t
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE* ^5 |: p% \3 F, n
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
# j5 c! u+ |" {2 F9 V1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design4 ?# E. a+ V5 E3 T) A/ @ ?
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
* ]6 e: a, n9 W: l9 u" W8 H3 ~1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long! T* \& x) D. }3 M* J' T& a4 ]
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
# a) E% K+ ?$ y- @1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
1 h; p! B4 m0 r4 w1258029 APD WIREBOND The bondwire lost after import the wire information4 K. G9 F3 q+ ^9 t& I; D
1258979 APD NC NC Drill: There is difference of number of drills." z* P8 e$ l9 T7 b/ U
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
# z' c1 E$ M, Y7 c! s# t- q1 ?1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.$ x) R) _0 d) q H* a4 A, J/ g
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer", v; a/ [9 S& Y+ f$ l* U9 e- B
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines# o! T5 P( C! u) h" a$ U( Y$ ^
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void* U3 \' S( e' B/ m7 P6 V
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
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