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SPB_16.6 27号补丁下载链接--Hotfix_SPB16.60.027_wint_1of1.exe

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发表于 2014-4-28 10:57:40 | 显示全部楼层 |阅读模式
27号补丁修复的BUG较多!  _6 P: t5 N' J4 G" S& m. c
百度网盘下载链接http://pan.baidu.com/s/1mgwSsPy
# q, K6 p7 o- \4 V$ o. `
& z# X5 v7 o8 H7 {+ tDATE: 04-25-2014   HOTFIX VERSION: 027
8 `1 m4 }6 Z' k3 D* G. o  g===================================================================================================================================. \9 M4 T) `, m3 [: D; R
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
2 K  m% O* l7 l===================================================================================================================================
* d3 Y3 J7 W8 v& Z. c308701  CONSTRAINT_MGR OTHER            Needs to delete user defined schedule in CM
. u, z3 O- g1 h; A. U) V* v  o( d7 u481674  allegro_EDITOR pads_IN          No board file saved from pads_in; y$ e9 m+ g( \
982929  allegro_EDITOR EDIT_ETCH        can't route on NC pin and other that are not pin.
! A9 f. Z( U& U& L" z6 X$ I1012783 FSP            OTHER            Need Undo Command in FSP4 P2 p6 F1 q* ~  G
1017381 ALLEGRO_EDITOR DRC_CONSTR       Need Dynamic Phase to be able to measure back to the Drive Pins.
2 b* r1 B* [9 J& M/ S/ x1072673 pcb_LIBRARIAN  GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
- h& A% t6 z/ V. ^5 S7 I1073231 CONCEPT_HDL    CORE             Copy-paste of signal names goes off-grid in Windows mode.
2 w; Q5 H& z8 n0 U. H# |1105371 CONCEPT_HDL    INTERFACE_DESIGN Strange behavior when shorting two Net groups
" t) J7 O! S0 q9 [- H& B( n2 C  Z4 j2 k1116498 CIS            LINK_DATABASE_PA link database with modified part results in Capture crash
( Z) W8 n& {; T  k9 A8 @9 {1118632 ALLEGRO_EDITOR GRAPHICS         Text display refresh issue while in Edit > text command
4 z0 v$ S1 k' D( p, }: f1155821 SIG_INTEGRITY  LIBRARY          Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode9 Z/ L5 s# a9 _5 }7 {* W3 r: L
1157372 ALLEGRO_EDITOR DRC_CONSTR       Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
4 a' L: t2 C& Z/ H, j6 i. V' ?- w- A1171951 ALLEGRO_EDITOR CREATE_SYM       Jumper has a limited of count when it add to list.& Q+ k+ Q0 U6 ?4 {" A. m2 V; b
1180871 CAPTURE        LIBRARY_EDITOR   Copied parts don't retain pin name and pin number settings- z0 j; M% V: G+ e
1185575 SIP_layout     DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
4 G! ^) e& ?% `2 M. D, E; K) Y1185772 PCB_LIBRARIAN  CORE             VALID_PACK_TYPE warning when cell was opened in PDV4 }2 @% @3 r( Z* A" T
1192377 CAPTURE        SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.0 t5 ]4 Y- q" r4 Z. E
1202654 ALLEGRO_EDITOR GRAPHICS         Zoom using mouse wheel shall maintain the center co-ordinates
* \& p, T8 @, D* b' e$ f. V1208031 ALLEGRO_EDITOR INTERACTIV       Snap to Pin for via during Copy command do not snap to connect point everytime: e9 }( E* X9 U+ _  ^' E4 f
1208478 PSPICE         PROBE            Attached project gives overflow error with marching ON.% h( V8 o3 }& l* k1 F
1210015 CONCEPT_HDL    CORE             The value of $PN should be not turned on spin or rotate symbol9 X! ^7 ?5 l$ v5 N0 }9 L/ c
1210425 CONCEPT_HDL    CORE             When moving a circuit tool reports that connectivity has changed
# n' @# \3 F$ y0 M* p: m3 s1215858 ALLEGRO_EDITOR SHAPE            Force update does not void cline with the shape
5 X& `* Q* J- w0 e1215906 ALLEGRO_EDITOR SHAPE            Dynamic shape fill smooth failed when copying to other layers
4 r. D3 X3 u5 d9 U' y- q$ N1216358 CONCEPT_HDL    CORE             Can we improve our export BOM function to check if user did export physical function before exporting BOM?
% G% J. b$ E3 ?0 ?1217364 CONCEPT_HDL    OTHER            Netlist reports fail because error: GScald failed.5 a& M3 R: d4 E" Z
1217529 CONCEPT_HDL    CORE             ADW checks do not catch single quotes in PTF values+ p+ I0 n- n  F/ o% c* C
1217556 F2B            PACKAGERXL       signal name change not sent to Allegro after packaging' C7 A- V; O% c" o0 G6 J5 ~
1219283 ALLEGRO_EDITOR DRC_CONSTR       Show constraint is inconsistent when displaying region information
& r) ^( O7 g" i6 |! h) V! k1220078 F2B            PACKAGERXL       Export Physical crashes when ALL the part pins are added
6 S  Y, ?7 |6 `1220393 CONSTRAINT_MGR CONCEPT_HDL      HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.) [0 I1 ]+ \9 J/ x8 w
1220540 ALLEGRO_EDITOR GRAPHICS         Need an option to see the pads inside the internal plane shapes- w9 h. U2 {9 u
1220936 CONCEPT_HDL    CORE             About crash by vpadd/vpdelete command on Linux/ Q( Z. o: n7 z$ n% z1 I- ~
1221059 ALLEGRO_EDITOR DRC_CONSTR       Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
4 w4 I* e/ D7 g2 ^" b+ r. Z1221182 ADW            TDA              Team Design with SAMBA2 w, N2 M: p- N; y8 x
1222442 CONSTRAINT_MGR UI_FORMS         Duplicate pin pairs appear in DiffPair# v# J$ _( @. ^; E9 l" n; g5 z
1223175 CONCEPT_HDL    CONSTRAINT_MGR   Schematic crashes when opened
& o. p$ d7 T" h, R; ~1223533 ALLEGRO_EDITOR GRAPHICS         Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
1 u! U/ U0 q+ z0 U" s1223680 CONSTRAINT_MGR ECS_APPLY        Improve ECSet mapping by allowing user to address ambiguity of Parts
+ L8 P  t) G# U$ L+ I1224156 SIG_INTEGRITY  SIGWAVE          Exporting spreadsheet with filter Subitems in SigWave exports all waveforms; A. E' m* M) {3 }7 S; ]
1224417 ALLEGRO_EDITOR PLOTTING         Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
) {3 w6 q$ ~# G4 r; E# @1224704 F2B            DESIGNVARI       There is no lock for the variant.dat file - multiple users can open the editor
/ g  N# H6 _( f/ O2 a9 i8 A9 g1224968 ALLEGRO_EDITOR INTERACTIV       Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
" f9 p& B. [( u4 n, o+ C, U1224982 CONCEPT_HDL    PDF              commandline publishpdf does not work when there are spaces in the path! U* M8 o0 v5 {; U, p
1225114 CAPTURE        GENERAL          H-pins added after netgroup pin get color as of netgroup pin
" T: n& I& K/ K- C1225494 CAPTURE        DRC              Different DRC results for Entire design and selection
$ Y% P4 H5 R; o' N" {3 ]) S! h1226153 ALLEGRO_EDITOR INTERFACES       Export STEP should include PART_NUMBER property0 W, G$ {6 w$ t: H4 W' m
1226235 ALLEGRO_EDITOR EDIT_ETCH        Enhancement to include Pin_delay of descrete forming Xnet, l" R# d( {$ y" x4 ~  D
1226372 CAPTURE        GENERATE_PART    ENH: Functionality to add pin spacing in New Part From Spreadsheet
% |; h1 y) U8 R8 Y  s) q% R6 X1226477 CONCEPT_HDL    CORE             DE HDL縮 `Allowed Global Shorts?  function is inconvenient for Global Signal- ^+ w. s  F$ E0 D/ M; }7 x% w
1226813 SIP_LAYOUT     LEFDEF_IF        ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file6 p: e% p: C% p3 D7 k! L
1227453 ALLEGRO_EDITOR SHAPE            Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors% \! C% J0 }2 L: G
1227461 ALLEGRO_EDITOR SHAPE            Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,88 f2 s1 T3 w, m; M( B2 X, N4 S
1227469 CIS            DBC_CFG_WIZARD   Oracle Views not visible on Step2 of CIS Configuration! F$ R2 B4 J) l: P5 P( K* `
1227780 CAPTURE        ANNOTATE         Inconsistent behaviour when annotating heterogeneous part- a: n. K5 Z8 \9 e5 S# G
1227831 CONCEPT_HDL    CORE             Pin text and H-block name in upper case) ?9 x0 E; Q9 ^7 h) _
1227954 CONCEPT_HDL    OTHER            supress check for global signals when wires are unconnected to pins
! h. y8 y4 B7 J5 o$ v. Z: J1228190 ALLEGRO_EDITOR OTHER            Unable to close the 'usage' window during license selection5 O: B& _1 U" t4 B( ]; p
1228899 CONSTRAINT_MGR INTERACTIV       Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
& G1 U7 |* X5 D" V; }. b& O) R1228934 ALLEGRO_EDITOR EDIT_ETCH        The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
9 v. G& J  f, w  b, v4 m, H$ m1229316 ALLEGRO_EDITOR EDIT_ETCH        When routing with Hug only enabled we were able to route through other routes(sometimes Hug).' K' ^# i7 O( q& T3 L1 {! k$ M
1229545 CONSTRAINT_MGR OTHER            Allegro indicate bundle scheduled nets in CM6 _  G! K. X3 e2 y. c& g# s; U# k
1230056 ALLEGRO_EDITOR GRAPHICS         Bug: 3D View of Mechanical Symbol with the drill hole defined3 f8 |$ E4 Z. T! v
1230432 CONCEPT_HDL    CORE             No Description information in BOM
) \4 m' p' U# R7 O1231148 F2B            DESIGNVARI       The variant.dat file is not updated with library PTF changes" z8 `& v$ G0 b: m4 Y0 p
1231625 F2B            DESIGNSYNC       VDD at command line needs to support sch2sch and test variable to write out report files
2 [" l* I1 n/ W. u( ]$ `: z1231697 CONCEPT_HDL    CORE             If any locked files exist force a pop-up dialog restricting certain commands9 B5 t1 \+ t. K) }0 z
1231767 CONCEPT_HDL    OTHER            Unable to find under the search options single bit vector nets
  X+ r& g! v! |  R: e( l1231961 ALLEGRO_EDITOR SHAPE            Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
7 o1 ]$ I7 l" X/ X: t. x1232100 CONCEPT_HDL    SKILL            Unable to execute the SKILL commands in viewer mode4 y  l# y8 \/ _: ~
1232336 CONSTRAINT_MGR CONCEPT_HDL      cmFeedback takes 5hrs to complete during Import Physical$ |4 D2 B& q! D0 q
1232710 F2B            DESIGNVARI       Dehdl crash while moving component in variant viewer mode
, ]7 |  _8 L4 A9 _0 Q0 X2 D1233894 F2B            PACKAGERXL       The page data is missing in the pst* and PCB files' c) r  C- J2 E: v& t8 J
1235785 CONCEPT_HDL    CREFER           cref_from_list custom text is not subsitituted in complex hierarchy
% |3 B2 K' E2 A" O5 M) o) e1235928 CAPTURE        SCHEMATIC_EDITOR OleObject modifications not saved# `% Z7 w( V# ?8 B
1236065 CAPTURE        PART_EDITOR      Mirrored part after being edited get pin name locations incorrect2 K7 B+ b/ D$ R+ V- Y  o2 i0 a
1236071 ALLEGRO_EDITOR SHAPE            Airgap for Octagonal Pads ignores DRC Value when Thermal set3 g  w1 U7 M0 B$ B0 r6 [; P# Z
1236072 CONCEPT_HDL    CORE             Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
+ b! v, e) [- m6 Y* }1236161 CONCEPT_HDL    CORE             Import Design shows the current project pages
  b6 O5 U% i$ i9 P$ I1236432 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translate via and shape in some instances.. _. l- _4 j4 f' r/ ]& @: m; \
1236557 CONCEPT_HDL    PDF              Running Publish PDF on command line in linux doesn't output progress until completion
+ `6 m1 c0 S7 R3 X/ [0 F' _7 U1236589 CONCEPT_HDL    PDF              Enhancement license failure error should appear in pdfpuplisher  log file
* r2 V, `) C- y9 c" Q* X: `1236644 ALLEGRO_EDITOR EDIT_ETCH        create fanout deletes shape
. [. I, _2 e8 e6 P4 J  q* h- f1236689 ALLEGRO_EDITOR GRAPHICS         Graphics displays extraneous lines when panning or zooming
7 m5 v( ?# K( t2 Q$ W1236781 F2B            PACKAGERXL       Export Physical produces empty files
( M/ O$ M; w8 Y, ~0 i8 R  b1237331 PSPICE         ENVIRONMENT      pspice.exe <cir file name> - hangs when run
% a" C' [8 x; G1237400 CIS            EXPLORER         Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
3 {+ u- [. T/ r+ R+ x$ ?+ c1237437 CONCEPT_HDL    CONSTRAINT_MGR   CM Crash when saving after restore from definition9 \3 s  d3 l9 z" X
1237862 CONSTRAINT_MGR OTHER            A way to remove the RAVEL markers from the Constraint Manager.( A2 W8 `2 h/ Y% Q# _3 A% n, g
1238852 CAPTURE        GENERAL          signal list not updated for buses
5 n- N0 S+ ~1 t0 t7 Q1238856 FSP            DE-HDL_SCHEMATIC FSP schematic generation crashes
& k+ ]$ q+ U& d8 J3 `1239079 ALLEGRO_EDITOR INTERACTIV       The 16.6 Padstack > Replace function leaves old padstack.! y9 E. x3 w1 {" h% a; J! d
1239706 CONSTRAINT_MGR ANALYSIS         The reflection result on a differential signal in the CM when Measurement location is DIE9 p! o8 `+ }) ~$ M" S. A
1239763 PSPICE         PROBE            Cannot modify text label if right y axis is active
% C. ~4 K; ^: `( l4 T* C1240276 ALLEGRO_EDITOR GRAPHICS         Printing to PDF from SigXp is giving unreadable images
5 F  y- ^; ?; f% B% o2 t) m3 e1240356 CAPTURE        IMPORT/EXPORT    Can縯 import SDT schematic to Capture.
7 u/ c5 l1 E' F: d/ d$ H9 p1240502 F2B            PACKAGERXL       Corrupt cfg_package does not stop PackagerXL from completing
6 u! I, ?3 A, |& H: }" |  ^. z1240607 ALLEGRO_EDITOR OTHER            Footprint of screw hole got shift in DXF file; u" f' W1 \0 P; y& h
1240670 ALLEGRO_EDITOR PLACEMENT        Select multiple parts and Rotate makes them immovable
" ]) o6 |6 j& }5 h. l* s  W1240773 CAPTURE        DRC              DRC check reports error for duplicate NetGroup Reference in complex hierarchy
( |* f: g0 _3 c) [# A: g8 s1240845 SIG_EXPLORER   EXTRACTTOP       Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
# i* Z$ d+ A# u1241634 ALLEGRO_EDITOR OTHER            Netshort for pad-pad connect not working
/ @# d; M! w! U$ s* @1241776 CONCEPT_HDL    CORE             In hierarchal design not all pages are getting printed.2 k0 y) y& q; ~0 u: o' q" R
1241788 CONSTRAINT_MGR CONCEPT_HDL      Issues with changing focus in Constraint manager using keys on keyboard" I/ U2 ^5 U8 ]/ _( S0 M! n
1242683 ALLEGRO_EDITOR INTERACTIV       Color View Save replaces file without warning7 I; ]9 |  X9 r5 T- u8 V- d: {
1242818 ALLEGRO_EDITOR PLACEMENT        Placement edit mirror option places component on wrong side. o* |8 A/ u) s' O  n
1242847 ALLEGRO_EDITOR GRAPHICS         Need an option to suppress Via Holes in 3D Viewer
" U# s8 d/ I! H+ u8 E1242923 ADW            COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results" q6 C- ^& u( `& W: R3 y6 A
1243609 CONCEPT_HDL    CORE             autoprop for occurrence properties
* g! m$ h* L: M. \. j3 Q1243682 F2B            DESIGNVARI       after undocking variant icon cannot be redocked back to GUI
2 l$ i& M! w3 _1243686 ALLEGRO_EDITOR GRAPHICS         Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
6 K8 Z/ {) E+ K" X8 @- e1243715 CAPTURE        PART_EDITOR      Pin name positioning get changed after rotating or mirroring- w1 o/ I, N; o/ @9 K
1244945 CONCEPT_HDL    PDF              PDF Publisher does not include image when file is not located in the root folder, S, y0 h2 m+ H0 d
1245568 CONCEPT_HDL    CORE             Dual unselect needed for wires attached to other net/source and property is not deselected when component is
+ T1 s6 ^. ]+ {; }. `, j( Q0 y1245819 F2B            PACKAGERXL       wrong injected properties information passed during packaging of the design
( R7 F' B8 ^" C: }+ I2 o  `: ~& ~  s1245916 SCM            CONCEPT_IMPORT   Where does the folder location reside for DEHDL imported blocks?
4 p: c$ D/ W& y+ ?% M, W! b1246347 CONSTRAINT_MGR CONCEPT_HDL      DEHDL crash if environment variable path has trailing backslash character
2 y; ~; `) A! ~/ q" r1246896 ALLEGRO_EDITOR DFA              DFA_UPDATE on Linux reports err message if the path has Upper case characters
6 t. ]! B5 A3 R2 Z5 s1247019 SIP_LAYOUT     DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
- {1 M3 B) N; q9 ]1247037 CAPTURE        LIBRARY_EDITOR   Copy & Paste of library parts resets pin name and number
. q$ i0 `: N) }  o! k; M- @1247089 CONCEPT_HDL    CORE             Group Align or Distribute > Left/Center/Right crashes DEHDL# Q" X1 N" I* W, x1 ?
1247163 CONCEPT_HDL    PDF              Physical Net Names in PDF not maintained6 `' T6 s' X7 r' P* H! B
1247462 CONCEPT_HDL    CORE             Text issue while moving with bounding box
& n: A" H9 R( ]" L1247464 ALLEGRO_EDITOR UI_FORMS         When using the define B/B via UI the end layer dropdown arrow is partially covered
) S/ n5 X/ q& ~' U1 X6 s1249063 CONCEPT_HDL    CONSTRAINT_MGR   CM and SigXP doesn縯 respect PACK_IGNORE at components1 ~1 ~; h, Y4 |2 }9 C7 r3 t
1250270 CONCEPT_HDL    CORE             Part Manager Update places wrong parts7 e/ w* o, q7 n
1251206 ALLEGRO_EDITOR ARTWORK          Aperture command cannot create appropriate aperture automatically from design.
! q& G( t9 C  i2 U# p' P: S1251356 ALLEGRO_EDITOR INTERFACES       Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
2 a; z# g- H! Z1251845 ALLEGRO_EDITOR EXTRACT          Crosshatch arcs do not extract correctly
+ n5 J+ A$ ?  N. l% `1 q6 O1 h1252143 APD            OTHER            When using the beta "shape to cline" command the tool is removing the shape instead of converting it.3 g9 s8 w8 F7 J5 |5 p5 ?- _0 a
1252737 SIP_LAYOUT     OTHER            SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies2 |# [2 P. S/ O& S& y9 L8 T
1253424 SCM            SCHGEN           Export Schematics Crashes System Architect
, w% ~" g2 [; n1253508 ALLEGRO_EDITOR INTERFACES       Bug - Export IPC2581 exports Crosshatch shapes as filled- c# C% O- T$ l- M9 E" D# y
1253554 SIP_LAYOUT     OTHER            SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing( ]0 z( R' d8 m3 U2 M
1254578 SPIF           OTHER            Specctra crash with Error -1073741819 for Auto router: g; M6 m1 j$ T' u% K
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK   adding nets to a net group causes constraint assignment error# ~; Z' Y3 ?6 `1 D
1254676 GRE            IFP_INTERACTIVE  Rake Lines disappear when Auto-Interactive Breakout is enabled.
" o1 s6 t" H4 k2 e1255067 SIG_INTEGRITY  REPORTS          Allegro hangs on Net Parasitc Report generation# _$ C  G; ~1 c: S2 Z
1255267 ALLEGRO_EDITOR SKILL            axlDBGetPropDictEntry does not return a list of all objects6 u* W# H5 k; [0 ~* j. }0 l6 X
1255383 SIP_LAYOUT     IC_IO_EDITING    cant move bumps or driver in app mode: Q8 f) |8 R. J( l" ~3 }
1255703 ALLEGRO_EDITOR SKILL            axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided7 J+ J0 r( n* V: ~+ `
1255759 ALLEGRO_EDITOR INTERFACES       Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
* c, L, Y, P: A$ E# V1256457 CONCEPT_HDL    CONSTRAINT_MGR   Extracting a XNet from CM crashes the tool
) g; x( {. I; y7 X1256597 GRE            CORE             Allegro GRE crashes while running Plan Spatial, on a particular design
' g* J# M7 V) R. j" Z2 k; S' P1256650 ASI_PI         GUI              PFE - Cannot generate model file error when using company decap library
; ^! p+ Z7 V# w0 |/ J/ a- L1256837 SIP_LAYOUT     DIE_EDITOR       Open and close of die editor takes too long
4 w6 g! d* F& F3 ^1257732 CONSTRAINT_MGR OTHER            Bug - Export Analysis Results in CM makes Allegro crash& g, C- c- k0 {# M5 d0 s
1257755 ALLEGRO_EDITOR OTHER            Editing time in Display > Status seems to be logging wrong time& R' q. |( v* d! }* I& f
1258029 APD            WIREBOND         The bondwire lost after import the wire information
5 v& h) M' V5 x4 R! e  E1258979 APD            NC               NC Drill: There is difference of number of drills.
" Q* P  ?8 O# O/ q& x1259484 SIP_LAYOUT     OTHER            SiP - calc min airgap calculate minimum airgap beta feature improvement
1 }  f4 f, y8 N% i7 y1259677 CONCEPT_HDL    CORE             hier_write -forcereset cause component prop change.
/ R; _6 C# O$ Y: F0 b1259913 ALLEGRO_EDITOR UI_FORMS         Unable to save setting of "use secondary step models in 3D viewer": k1 o2 [; K5 _9 O1 ~
1261758 ALLEGRO_EDITOR EDIT_ETCH        Auto Interactive Delay tune (AiDT) is deleting clines- ]7 C( f6 p5 d
1262543 ALLEGRO_EDITOR MANUFACT         merge shape results in moved void
( K2 Z: P, i8 G/ N: F, ]) D1264767 ALLEGRO_EDITOR DRC_TIMING_CHK   XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss' Q% F4 m" Q! z! H5 W, Z3 j

4 p7 x+ @1 ^! Q+ g( b
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