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Loading... E:\allegroXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstchip.dat; _7 M0 ?& n2 y/ ~, t( H
( E O' f. t3 k" [+ e* nLoading... E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstchip.dat) ^" p g; ^( y* R
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Loading... E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstxprt.dat
1 f" {6 ~8 z! O#77 ERROR(SPCODD-77): Could not open file E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstxprt.dat.
5 ?+ o9 T( x1 V$ o* }You might be trying to reuse a design with an inaccessible state file. To reuse a design, ensure that the design being reused is treated as a subdesign and the subdesign state file is accessible and readable. To create the subdesign state file, use the GEN_SUBDESIGN directive.' {& q) C9 [8 R& R6 ]
ERROR(SPCODD-382): Error at line 1 in file E:\ALLEGROXUEXI20210218\ALLEGROLIANXI20210216\SCH\ZHONGJIBAN\allegro/pstxprt.dat. Error loading the parts list file+ J4 d+ M6 ~& O! B0 ]
- Q0 l( \+ l* ~& Y#292 ERROR(ORCAP-36026): Unable to read logical netlist data.: u9 M+ B3 W" M4 n, K# Z: @% p
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- C% }$ s) c( Lorcad在导网表时出现打不开pstxprt.dat文件,在Allegro文件下不能找到该文件,不知道为什么没有生成,恳请大佬帮助一下。' r5 D( o) ~" Z9 ~" z9 Y
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