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发表于 2023-4-3 18:30:57
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Switch mode regulators
. T' C b( p7 d3 b" k: qQCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
' N9 K3 b, G. h3 ^; f, Nreceive power from VBAT or VCHG under application software control.2 P3 b: ?1 y2 ~
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040* t6 x4 H5 ^$ j
VFBGA and the flash memory. The System SMPS can supply power to external components.: D# }! b7 N; A
The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches5 b2 F' _+ K- G8 }$ m% y
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
7 q6 m. N2 m0 d# rThe SMPS both have three operating modes:
- b$ w% [4 D) j8 O& V4 ?■ Normal (PWM)8 T% ^! x! N" d4 t5 h' `1 ]
■ Two low-power modes with reduced current capability:
6 X- M4 v& S, y□ PFM
$ b x+ A6 e- \. o□ ULP
: p. S5 [5 }# GNormally the system auto switches, but this is optionally disabled.. y6 h2 e+ J7 `. e1 A7 l
The SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor. S* G2 l, w9 m7 Q
For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-& P; D5 R6 |5 }1 j+ f' v$ r
CH285-1).
3 N' w- }& B6 x/ l, i0 lA single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have
4 `9 N, g, U* ~4 ?a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point./ C ~0 o7 r2 q5 a4 w/ }
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.1 l( E' Y9 Q }6 p4 c
% s+ i, j: p* r4 P, \% ] Z2 P |
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