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发表于 2023-4-3 18:30:57
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Switch mode regulators4 t' M M$ z% c9 M; H
QCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators% ^( M, m2 w/ j! x# ]
receive power from VBAT or VCHG under application software control.# {5 s9 V2 x4 e7 V$ P9 k/ Z
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040
$ U i5 f7 Z. AVFBGA and the flash memory. The System SMPS can supply power to external components.
* q( u! q& }! c5 K+ RThe digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches
1 }0 S# a/ z. h2 X8 k0 ^between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
1 u9 a7 Q+ C* b1 r; J) _3 p' RThe SMPS both have three operating modes:9 m: Y. y3 }( K" h$ H0 U9 y
■ Normal (PWM)
# z. H6 k6 u+ j& a■ Two low-power modes with reduced current capability:
/ `0 q& M- N0 \- c7 X□ PFM# k @0 s( u, F9 q5 G& m
□ ULP4 x4 o8 a( m0 N5 D3 A
Normally the system auto switches, but this is optionally disabled.
3 z9 H; \0 v4 z$ p: m( t1 lThe SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.* P* S5 X6 _, _! u/ f, v+ `
For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-( [9 w R6 y% S2 A- \+ X1 ]4 i5 ^
CH285-1).8 m+ N. ?2 ^ ], s' [& a( W
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have" |1 Y, I' y; b4 F
a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.2 w# g; ^# t1 J& o7 A5 U
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG., z' {9 k3 I9 ^# ]+ u
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