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发表于 2023-4-3 18:30:57
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Switch mode regulators
! m' J; z% X8 \4 W+ P; Z2 ~3 mQCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
" ~) X" L) @1 yreceive power from VBAT or VCHG under application software control.
- ^. I0 x7 G# D# p6 T- EThe System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040( ] @4 I) |( t" N4 P
VFBGA and the flash memory. The System SMPS can supply power to external components." ^7 e* D$ t5 `) b
The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches* O" Q# G$ g e' v0 [
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.9 X, B; K4 ]! ^5 Y8 Q
The SMPS both have three operating modes:' |4 z7 W' A! z! M4 r+ F/ C7 _
■ Normal (PWM)
$ j; t) t2 |% f v■ Two low-power modes with reduced current capability:1 _) ]: m8 Z8 m7 Z
□ PFM0 z) [/ _/ C9 J. H7 I$ Z* @
□ ULP# ^& F# A1 A3 I1 K b
Normally the system auto switches, but this is optionally disabled.
& s+ s$ a' F, K& k' V9 P% i2 f) nThe SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.4 o) j$ K- e2 E' v
For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-
% w( M4 d1 C) M6 u) g) e$ YCH285-1).0 |7 u! f) B% T8 T6 K9 X
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have% ^4 r" G) t3 R! n+ t: b( v
a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.- X: p9 y) O t$ d4 K
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
# z& L, V: Y i6 \2 U! k0 `8 v1 W% o% b2 D3 P$ g
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