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发表于 2023-4-3 18:30:57
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Switch mode regulators7 g% s. H; C3 f7 h( c
QCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
7 P# V9 I% x5 Ireceive power from VBAT or VCHG under application software control.8 U, q' a; [7 r B- w; O. Z, t {
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040
3 |1 ]* i r: [& g2 L4 f. HVFBGA and the flash memory. The System SMPS can supply power to external components.
/ H6 h1 j H2 d* g fThe digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches+ F E. s7 y& l/ a! f% ?+ A
between 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
2 x; l3 m. `; JThe SMPS both have three operating modes:% R2 d5 W9 r0 @. P! Z3 R/ @' u
■ Normal (PWM)/ E( q, T7 J) j( O: e
■ Two low-power modes with reduced current capability:
2 t" E6 z2 Y% W( z. c4 r+ Q□ PFM
; k m; l! H: K! S9 i□ ULP9 q% V" e) k* Y9 r" k
Normally the system auto switches, but this is optionally disabled.- r% p+ j# Z# l' g1 |2 b
The SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.
/ z- B& b2 k8 F: i2 ~For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-/ D+ \& M# _0 v- b u
CH285-1).
3 \& [( K9 f& QA single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have8 W- G$ c5 f& X2 @
a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.+ n5 J: G8 ~+ V2 s( Z ^
The SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
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