【PDF教程】电子元器件选型规范教程

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fanyijiaoyu2023

yummy 发表于 2021-10-13 14:01
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肖红军

This application note is intended to provide recommendations concerning incorporation of circuit
3 L* c7 v) @. M) Wprotection devices and PCB layout guidelines to enhance an application's immunity in electrically noisy
environments and survivability of EMI, EMC, EFT, and ESD events as described in the International
Electrotechnical Commission (IEC) standards: IEC 61000-4-2, IEC 61000-4-4, and IEC 61000-4-5.
We will begin with:
1. A brief review of EMI, EFT, and ESD specifications.
% e% d- l0 O/ f+ N: ^5 s2. Key ESD protection device specifications definitions.
3. A quick summary of EMI, EFT, and ESD protection strategies.
6 f& o0 Q- {; V- T/ j) D4 I4. Capacitor filter selection and characteristics.
2 w9 _. ~! a% H4 I! S7 C2 ^5. PCB Hardware design best practices and layout considerations checklists:
2 w" f6 n2 M; ^1 v& q– Standard PCB design/layout practices
– Special Ethernet layout considerations
* A. Z3 o0 v1 \& d– Special DDR Layout considerations
6. Software protection techniques.
7. Microcontroller reference circuit schematics with protection examples:
– RS-232
0 y; }9 ]. C( n" N" r– USB
2 ~" Z$ O5 b$ o2 J' T3 E" f! U– CAN FD and LIN
– Ethernet
5 J4 q5 ?; E5 @– Audio and mechanical switches
- a9 [. q5 s8 Y. R– LCD
– Power supplies
– Reset and ICSP programming interface
$ w. ?9 x% L& X( K– SD memory card
– I2C
Reference Designs Note:
Cost pressure is a constant consideration in any design. All of the circuit components in support of the
/ ^1 q6 J$ Y: v9 ZCPU were selected based on the lowest cost and availability, which met the threat protection
: n! X" P9 R# y" |requirements. A user should carefully consider any substitutions. It is also highly recommended that the
& m+ \( u2 n( b) ?( k! J: ]% guser consider designing in the protection elements in their layout, and then depopulate with zero ohm
; i( ^" K4 \2 [2 Zresistors as they think necessary, based on ESD, EMI, and EFT prototype board testing. This will save
: M, C  V1 K* _1 d7 r1 ^& hsignificant board redesign time to market in the final product.

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