IP核的使用有什么要求吗

张翔10

刚接触Verilog不久，需要做个FPGA解二阶微分方程。
! Y0 y( \+ z7 r# y" e2 e2 c我用欧拉法解得，但调用IP核总是出毛病
比如
Error (10170): Verilog HDL syntax error at Eeler.v(22) near text "add_sub_inst";  expecting "<=", or "="
" ]" _/ p: J) a# J+ e0 r: a: kError (10149): Verilog HDL Declaration error at Eeler.v(25): identifier "mult_inst" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at Eeler.v(26): identifier "add_sub_inst" is already declared in the present scope
5 w3 T) \9 x& v9 _9 NError (10149): Verilog HDL Declaration error at Eeler.v(27): identifier "mult_inst" is already declared in the present scope
Error (10149): Verilog HDL Declaration error at Eeler.v(28): identifier "add_sub_inst" is already declared in the present scope
! w1 u- T0 c1 |% H7 v! dError (10170): Verilog HDL syntax error at Eeler.v(30) near text "$display";  expecting "endmodule"
/ ]5 y1 h( Z- MError (10759): Verilog HDL error at Eeler.v(30): object x declared in a list of port declarations cannot be redeclared within the module body
' D+ i: {% J! kError (10759): Verilog HDL error at Eeler.v(30): object y declared in a list of port declarations cannot be redeclared within the module body
/ z) W# G4 j! tError (10759): Verilog HDL error at Eeler.v(30): object z declared in a list of port declarations cannot be redeclared within the module body
0 l" a8 r8 m; CError (10170): Verilog HDL syntax error at Eeler.v(30) near text ")";  expecting ";"
Error (10112): Ignored design unit "Eeler" at Eeler.v(1) due to previous errors
/ T2 B3 b7 {0 k6 y编的源程序这样
0 y. s- q9 }5 A4 O  t& qmodule Euler
(
+ {  `/ ]5 a' x! x) M  Pinput wire           clk,
input wire    [31:0]   x,      //定义输入量，单精度32位浮点数
: X0 Y' m6 e* _0 M# U* ?input wire    [31:0]   y,
* }- L/ M1 L8 t  _8 g: t2 oinput wire    [31:0]   z,
input wire    [31:0]   h,
7 L5 k8 m* @. j9 v2 B) d5 youtput wire    n1
);




6 x0 A. S( A3 R0 Yreg[31:0] z11;
reg[31:0] z1;
reg[31:0] y11;
! p2 A( f3 [3 _! n6 J% preg[31:0] y12;
integer n;
6 J7 s' e- \0 J
9 @4 ]% p9 ]% S' D) E& k
initial
1 D, Y2 W. q7 L //开始迭代
9 u* r( C% _1 o7 \$ Cfor (n = 0; n < 10; n=n+1)      
add_sub add_sub_inst( .clock ( clk),  .dataa ( x ),.datab ( h ),.result ( x ));
6 [* O. Y8 y" X; w- Xmult mult_inst( .clock ( clk ),  .dataa ( x),.datab ( z ),.result ( z11 ));            
add_sub add_sub_inst( .clock ( clk),  .dataa ( z11 ),.datab ( y ),.result ( z1 ) );      
+ _6 }( E2 K" v( M7 @mult mult_inst( .clock ( clk ),  .dataa ( h),.datab ( z),.result ( y11 ) );         
7 f; M$ A- g2 q5 [6 O# ]3 u1 iadd_sub add_sub_inst( .clock ( clk),  .dataa ( y ),.datab ( y11 ),.result ( y ) );   
mult mult_inst( .clock ( clk ),  .dataa (h),.datab ( z1 ),.result ( z12 ));         
add_sub add_sub_inst( .clock ( clk),  .dataa ( z ),.datab ( z12 ),.result ( z ) );
0 \$ W- y7 u6 }0 p6 @9 x

$ r( A5 e) K: E( p: s4 E$display ("n=%d x=%b  y=%b z=%b\n",n,x,y,z );
! P/ J6 f7 b9 r. a* z; f  Lendmodule
想问一下，是IP调用有问题吗？还是IP核不能在循环或函数里调用

xiaozhubanna

用另一种方式也有问题
module Euler
1 _' o, Q0 }$ i  m(
. v' m* l; n. D3 _% Dinput wire           clk,
input wire    [31:0]   x,      //定义输入量，单精度32位浮点数
, P& R4 i. k4 l8 dinput wire    [31:0]   y,
input wire    [31:0]   z,
input wire    [31:0]   h,
4 l% e6 X# e- W! q) S! z3 ?3 aoutput wire    n1
);


function   [31:0]   g;//加法器函数
& j7 w% o( X- ]5 R  input   reg   [31:0]   x;
  input   reg   [31:0]   y;
2 I( ^  {3 o$ n          reg   [31:0]   z;  
6 o5 @+ Q( E5 K& u, tbegin         
' D6 b$ e: H" kadd_sub add_sub_inst(
   //调用浮点数加法IP
.clock ( clk),
; P7 O, z# t1 d( e9 `9 y.dataa ( x ),
& z6 d6 R: M0 K.datab ( y ),
.result ( z )
    );
    g    =    z;
7 u& R* m0 S! z" ~8 Q' D& jend
- |; c! @. b) [4 wendfunction
7 _# K) d* a& X1 ?" y


- }( t. z& H6 x' U- U4 [
function[31:0]f;       //乘法器函数
0 g% h9 S9 W2 V1 c/ d2 _  input reg [31:0]x;
$ |0 [/ o5 T6 H4 u% g6 \* V5 y  input reg [31:0]y;
   reg [31:0]z;
begin   
4 v% j9 E$ v! I! |# a' [( }  Umult mult_inst(
7 q6 c$ i. z4 A9 \2 C5 N  //调用浮点数乘法IP
1 K5 G8 R' [& O( O% X; W  s7 d; L.clock ( clk ),
. `- o0 K) c8 X! q8 T$ M3 z; M.dataa ( x),
.datab ( y ),
6 c5 Q0 P! {! g8 T4 Y, W& I) |: b3 C.result ( z )
6 n$ S6 B5 o( m( {  Z3 q, c );
  f = z;
end
endfunction


reg[31:0] z11;
reg[31:0] z1;
reg[31:0] y11;
reg[31:0] y12;
& M2 R2 y: ?! r3 T/ f" A. g% Yinteger n;


initial
: f  D( P  L$ K1 |* tbegin
$ B# p9 a& `6 c8 q6 @4 W                     //开始迭代
0 N6 T' B: b2 v- rfor (n = 0; n < 10; n=n+1)
      begin
% E0 s0 m4 g4 F% \; t        x   = g(x,h);
        z11 = f(x,z);
        z1  = g(z11,y);
& K$ Z' E- {2 u; ^9 p        y11 = f(h,z);
        y   = g(y,y11);
        z12 = f(h,z1);
        z   = g(z,z12);
1 m! k. b$ {  u) b5 J       $display ("n=%d x=%b  y=%b z=%b\n",n,x,y,z );
      end
end
# h! R; A" Q/ N9 }endmodule
错误报告是
Error (10170): Verilog HDL syntax error at Eeler.v(16) near text "(";  expecting ";"
Error (10170): Verilog HDL syntax error at Eeler.v(33) near text "(";  expecting ";"
Error (10112): Ignored design unit "Euler" at Eeler.v(1) due to previous errors