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module nums(input [1:0]a,output reg [3:0]n);
( t# e* G8 y2 z8 d! k! Lalways@(*)begin% `8 G3 g/ N! a8 N: e+ b/ M
case(a)+ s8 |7 i4 j! _( U
0: n=4'b1111;
( ?- U7 }8 }# B' X. [ 1: n=4'b1010;
/ @5 Y1 d6 g8 B4 {8 a% X& T 2: n=4'b1110;
8 M$ u& E3 W% F9 Z2 B 3: n=4'b1001;/ f/ M+ P! r9 F% `" g0 W; h# e7 f2 J
default n=0;
, ?1 X0 l: c& J0 } endcase
u Z z2 v. Z4 }* dend
/ t3 C' u3 I+ s; m$ D: u" f0 xendmodule" |0 ^2 ?" ~+ k) z) J% K& {5 I
0 k0 {5 l2 T- L* b7 T0 \# C3 q; D
6 J9 H0 c. p" C5 o- F% W* Bmodule top (input k0,input k1,output [3:0]leds);9 p# x1 [' X. H2 L
wire keys[1:0];
. o0 F; `% p; t7 X9 `wire led[3:0];. z1 y1 y: f+ x ^9 O) D4 o! l. \
assign keys[0]=~k0;7 [6 `. H4 a; e; L: A
assign keys[1]=~k1;0 e2 E* [* t9 l) c) ~* x
nums(keys,leds);
/ u; U7 @2 m. O) P/ ]$ @) m8 Dendmodule |
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