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分享:最新Hotfix_SPB17.20.022_wint_1of1补丁

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发表于 2017-6-30 08:36:09 | 显示全部楼层 |阅读模式
Fixed CCRs: SPB 17.2 HF022% Y! C7 \! h* ^$ b* K* O# h
06-16-2017  o1 T; \5 U5 L: N2 Z! B
! c6 \# w) ]& B' Z8 t3 j0 [========================================================================================================================================================$ S8 c! [/ }7 ?) @1 D5 b7 i
CCRID   Product            ProductLevel2 Title% k0 a9 ~. B+ ]" p6 B, O: x  N2 X: t5 J
========================================================================================================================================================9 [5 Y+ x, m: |1 h) L2 Z. e, s* W0 n6 m5 e2 Z( p( B! Z
1755789 ADW                DBEDITOR      Checking in HSS Block returns 'Failed to create archive'4 {9 D& R, W) y) `2 |
1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager2 D, w* b% E. B1 w" X& h2 s$ i6 |: p! e6 Z7 U8 g" c/ T1 E& c
1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager! U6 A$ x# f0 E3 z
1744081 ADW                FLOW_MGR      Error regarding configuration file when trying to open Workflow Manager+ y  |% ]! O/ [1 N0 b
1756727 ADW                LIBIMPORT     EDM Library Import fails with java exceptions when merging classifications0 Q6 H* ^" t9 U+ C$ x! u: j
1743763 ADW                SRM           Find filter is grayed out when allegro PCB Editor is opened from EDM Flow Manager
# a" e! s+ ~6 P  r1748399 ALLEGRO_EDITOR     DATABASE      In release 17.2-2016, end caps not visible for certain clines in PCB Editor0 |7 \2 O: |  T# c0 X7 j- O, [+ g+ c! V1 ~
1748522 ALLEGRO_EDITOR     INTERACTIV    A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it% G: i) o* ]: q% B  x, U$ G" h: W' M
1734983 ALLEGRO_EDITOR     INTERFACES    Secondary step model does not stay mapped after drawing is reopened5 Z4 E; p  n. M! m0 h0 a
1753704 ALLEGRO_EDITOR     REFRESH       Refreshing symbols crashes PCB Editor0 z( R3 a, f2 g  x7 @0 A% |4 X8 m* {
1493721 ALLEGRO_EDITOR     SHAPE         Voids on negative planes are not adhering to constraints
- \6 ~1 K' P5 \6 z( d% M1711242 ALLEGRO_EDITOR     SHAPE         Route keep out leads to partly unfilled shapes with gaps* W' E' Z2 c6 K3 W) J1 [  ~- F5 }3 v( ]9 T
1726865 ALLEGRO_EDITOR     UI_GENERAL    Pop-up Mirror command does not mirror at cursor position: V' }! V: o6 c3 B8 b* k
9 ~) ^8 }4 o( H$ G1752987 ALLEGRO_EDITOR     UI_GENERAL    axlUIViewFileCreate zoom to xy location not working while in user created form.1 A' [, s' q4 m* w$ n. ^
1755638 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
( L  W: X7 Y3 K! h& ~1719792 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC hangs or crashes PCB Editor
2 g! N! _  ^) P6 r8 [, F/ D1624869 ALTM_TRANSLATOR    CAPTURE       A structure file is required to translate a third-party schematic to orcad Capture5 h) N& {5 y# @
6 c( [6 Q2 I. ?3 E& O" f2 D0 u4 S5 U1707416 ALTM_TRANSLATOR    CAPTURE       Missing components and pins in the OrCAD Capture schematic translated from a third-party tool0 j( ^; C0 R  L. N# A+ y. s
1708825 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate the schematic+ C9 ]1 Y, w4 s
6 g! G  j) J. I- h2 K. g5 h1719200 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate all the pages of a schematic  R' o7 z7 a$ k: @- o+ o" L. ~
1546070 ALTM_TRANSLATOR    CORE          Third-party to DE-HDL schematic translation fails4 B1 C. ]  f# |, ~) R8 P* `  x7 G' }6 ~& f# N4 r  U1 b- I
1700508 ALTM_TRANSLATOR    CORE          Third-party PCB translator does not work in release 17.2-2016
2 L- B- ?9 f8 x/ s0 K5 a1699340 ALTM_TRANSLATOR    DE_HDL        Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor3 i( w& }" I: n
1630379 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator is not importing clines and vias+ M6 w# P. r% o4 N/ h4 X( M: E4 X, {" n# ~
1708615 ALTM_TRANSLATOR    PCB_EDITOR    All items of third-party PCB not imported in release 17.2-20165 K; p5 P) [( l; r* |: ~6 ^: ^  l" s. C6 D  E% ~: o
1758296 APD                DXF_IF        DXF OUT: Rounded rectangle pads mirrored incorrectly
8 c& H9 _  j2 c( I1756040 APD                IMPORT_DATA   The 'die text in' command ignores values after the decimal point; p3 O7 w) ~/ K# ^; u7 ^- D* _- H; \* n: {0 [+ G! |
1727206 APD                SHAPE         Merging two shapes results in an incorrect shape. b7 j$ \$ h; f0 e+ r+ k0 a5 a' B( A2 a$ q) O( X+ c4 C& j
1753682 CONCEPT_HDL        CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL/ m7 G2 _1 g2 a% ~) s$ r/ n: U( R
1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic
6 I3 l/ F6 ^7 W+ C- ]5 R  ~1747559 CONCEPT_HDL        CORE          Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)9 P' k2 i6 F, w) N% Y' b4 H; j
8 z. `, G$ Z' P4 x1749644 CONCEPT_HDL        CORE          In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
3 _8 `  Z  y9 K9 p8 _+ u1746910 CONCEPT_HDL        GLOBALCHANGE  Global Component Change unable to identify part data when using schematic pick option) g1 d% F: {9 T; v# V; J2 }) S( u: o4 K' e
1743572 FLOWS              PROJMGR       Project Manager displays incorrect values in Project Setting1 _1 M4 m; C, x: }1 X& g! H. ]
; Q9 Z! J& g" Y8 P/ g2 H1724124 FSP                DESIGN_EXPLOR Provide TCL command to filter design connectivity window) c! K1 Y' J3 Z1 C* \5 B9 q1 V; ~7 I% _
1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner
# u* O4 @) r( {3 M) b1755750 PCB_LIBRARIAN      GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor9 ~$ M/ J6 A7 ]8 d: @8 x- Q* z
1722993 PCB_LIBRARIAN      IMPORT_CSV    Part Developer crashes while importing part information stored in a .csv file# V, A  b0 p% h7 A  p; ?! B
* P0 k( A- R' h1758856 SIP_layout         3D_VIEWER     Correct the spelling error in the 3D Viewer Design Configuration window' m. x) g8 u0 Z; B) B* g$ {% _' j- o5 v+ \; v" C) m) X; j
1755179 SIP_LAYOUT         ARTWORK       PCB Editor crashes when creating Gerber files# \8 x4 c0 g- o7 q& O
/ T$ C) z5 A+ O4 C, r  q( `& G1743511 SIP_LAYOUT         MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check* s0 M- l# f  ]$ x* ], Q. H2 d( S, K

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0 A- s7 O% |; @; z  R6 o( P链接:http://pan.baidu.com/s/1dFw4emH 密码:smbg
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发表于 2022-5-10 09:14:55 | 显示全部楼层
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