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分享:最新Hotfix_SPB17.20.022_wint_1of1补丁

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发表于 2017-6-30 08:36:09 | 显示全部楼层 |阅读模式
Fixed CCRs: SPB 17.2 HF022
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========================================================================================================================================================$ G1 m% F0 i7 ^
CCRID   Product            ProductLevel2 Title% k0 a9 ~. B+ ]" p6 B
2 A* C- K$ \6 M0 E, f- o  S========================================================================================================================================================9 [5 Y+ x, m: |1 h) L2 Z. e, s6 d9 H( j: H+ t1 r% Z. l1 S
1755789 ADW                DBEDITOR      Checking in HSS Block returns 'Failed to create archive'
: X' `* B+ ~, N1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager2 D, w* b% E. B1 w" X& h2 s$ i6 |: p! e6 Z# ~3 D& g0 u+ v1 `% ~+ W* O
1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager. g' c* w: w! D/ m) B# R
1744081 ADW                FLOW_MGR      Error regarding configuration file when trying to open Workflow Manager
0 y( q7 m! r0 n9 V" I2 U# u1756727 ADW                LIBIMPORT     EDM Library Import fails with java exceptions when merging classifications
* J8 D3 v1 |( z7 J1743763 ADW                SRM           Find filter is grayed out when allegro PCB Editor is opened from EDM Flow Manager7 G9 Z4 i7 B) @( c8 y& v2 t
1748399 ALLEGRO_EDITOR     DATABASE      In release 17.2-2016, end caps not visible for certain clines in PCB Editor0 |7 \2 O: |  T# c0 X
9 b# [# p& l2 Y( F: E) b8 F8 u! q$ E1748522 ALLEGRO_EDITOR     INTERACTIV    A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it% G: i) o* ]: q% B0 i7 L) g) @2 g5 \3 k/ _; ~% G
1734983 ALLEGRO_EDITOR     INTERFACES    Secondary step model does not stay mapped after drawing is reopened; l0 i4 _) _6 z( Q( o
1753704 ALLEGRO_EDITOR     REFRESH       Refreshing symbols crashes PCB Editor0 z( R3 a, f2 g" R& N+ G# T( \
1493721 ALLEGRO_EDITOR     SHAPE         Voids on negative planes are not adhering to constraints8 p1 z7 d5 S& k- }) i
1711242 ALLEGRO_EDITOR     SHAPE         Route keep out leads to partly unfilled shapes with gaps* W' E' Z2 c6 K3 W) J1 [
6 l& i, I* z8 r1726865 ALLEGRO_EDITOR     UI_GENERAL    Pop-up Mirror command does not mirror at cursor position: V' }! V: o6 c3 B8 b* k% X/ K/ H$ V1 E5 U1 G  p. \
1752987 ALLEGRO_EDITOR     UI_GENERAL    axlUIViewFileCreate zoom to xy location not working while in user created form." }: k3 Q$ x: x, P
1755638 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run4 c" l+ {& P* e$ K$ U
1719792 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC hangs or crashes PCB Editor
* c; Z4 ]3 m5 W5 A/ e8 v1624869 ALTM_TRANSLATOR    CAPTURE       A structure file is required to translate a third-party schematic to orcad Capture5 h) N& {5 y# @
5 {1 o" g/ K( E4 R* f) h1707416 ALTM_TRANSLATOR    CAPTURE       Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
! d2 Z/ R7 B  n1 o1708825 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate the schematic+ C9 ]1 Y, w4 s
* Z* g6 s3 j, N( q1 [4 H( x1719200 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate all the pages of a schematic
4 U7 y8 e7 }0 @5 E+ z1546070 ALTM_TRANSLATOR    CORE          Third-party to DE-HDL schematic translation fails4 B1 C. ]  f# |, ~) R8 P
3 t' W" C- y) v) A2 W& W: X1700508 ALTM_TRANSLATOR    CORE          Third-party PCB translator does not work in release 17.2-2016
& B+ D. a# f* C- [9 j8 f# I& x4 A1699340 ALTM_TRANSLATOR    DE_HDL        Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor! i- ?/ u6 c6 e( W3 K
1630379 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator is not importing clines and vias+ M6 w# P. r% o4 N/ h' a, b8 k; i% i0 s" u* P
1708615 ALTM_TRANSLATOR    PCB_EDITOR    All items of third-party PCB not imported in release 17.2-20165 K; p5 P) [( l; r* |: ~6 ^: ^
2 t( x4 d1 u$ q+ c3 Z2 \' |5 e! o1758296 APD                DXF_IF        DXF OUT: Rounded rectangle pads mirrored incorrectly4 o; g. r/ z: l/ e# l
1756040 APD                IMPORT_DATA   The 'die text in' command ignores values after the decimal point; p3 O7 w) ~/ K# ^; u7 ^- D* _- H: `* n/ Y6 ?3 R7 r0 t/ h" V
1727206 APD                SHAPE         Merging two shapes results in an incorrect shape. b7 j$ \$ h; f0 e+ r+ k0 a5 a' B
# I2 |( b3 _) X" J$ P1753682 CONCEPT_HDL        CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
) W9 P8 L, T: c( y7 R; D; v1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic; ?" L; H  y$ ?1 d' W" X2 n! a
1747559 CONCEPT_HDL        CORE          Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)9 P' k2 i6 F, w) N% Y' b4 H; j5 ]  Y, I7 N7 o* W. t1 g- o& ^+ `
1749644 CONCEPT_HDL        CORE          In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
, L: j7 m/ S3 b" m1746910 CONCEPT_HDL        GLOBALCHANGE  Global Component Change unable to identify part data when using schematic pick option) g1 d% F: {9 T; v# V; J: o: i8 E0 x) b5 i2 y4 L
1743572 FLOWS              PROJMGR       Project Manager displays incorrect values in Project Setting1 _1 M4 m; C, x: }1 X& g! H. ]4 _- k+ |8 B% H1 J1 R
1724124 FSP                DESIGN_EXPLOR Provide TCL command to filter design connectivity window) c! K1 Y' J3 Z1 C* \
: Z/ t" C7 C/ {; m, N1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner" ~' h" o6 ^" B$ J) Y4 c
1755750 PCB_LIBRARIAN      GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor4 y8 L6 V$ G+ U/ t
1722993 PCB_LIBRARIAN      IMPORT_CSV    Part Developer crashes while importing part information stored in a .csv file# V, A  b0 p% h7 A  p; ?! B. r  g% R+ J2 S8 F; T
1758856 SIP_layout         3D_VIEWER     Correct the spelling error in the 3D Viewer Design Configuration window' m. x) g8 u0 Z; B) B* g$ {7 Z5 N* E2 n2 y) c# D
1755179 SIP_LAYOUT         ARTWORK       PCB Editor crashes when creating Gerber files# \8 x4 c0 g- o7 q& O
1 r2 N% s5 s  f: j1743511 SIP_LAYOUT         MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
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发表于 2022-5-10 09:14:55 | 显示全部楼层
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