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分享:最新Hotfix_SPB17.20.022_wint_1of1补丁

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发表于 2017-6-30 08:36:09 | 显示全部楼层 |阅读模式
Fixed CCRs: SPB 17.2 HF0225 @: ^" n0 f: t2 l& @
06-16-2017  o1 T; \5 U5 L: N2 Z! B4 E# [1 c6 `& |" z1 r
========================================================================================================================================================
' u' S, E7 u/ H; ?- L+ ^* LCCRID   Product            ProductLevel2 Title% k0 a9 ~. B+ ]" p6 B
# @8 B$ ^7 a% ]========================================================================================================================================================9 [5 Y+ x, m: |1 h) L2 Z. e, s1 Q+ D6 p. P; P$ t
1755789 ADW                DBEDITOR      Checking in HSS Block returns 'Failed to create archive'
% K2 L/ z3 T2 Q* n/ c* m, s1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager2 D, w* b% E. B1 w" X& h2 s$ i6 |: p! e6 Z8 g% V* K) K% z+ w; [" ?- k" s
1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager! l; X0 I$ G" l. }- J. j
1744081 ADW                FLOW_MGR      Error regarding configuration file when trying to open Workflow Manager9 J0 }7 J. t. G- c0 x
1756727 ADW                LIBIMPORT     EDM Library Import fails with java exceptions when merging classifications
: r+ \' B3 S! r) D) ^1743763 ADW                SRM           Find filter is grayed out when allegro PCB Editor is opened from EDM Flow Manager& [6 p7 D3 ]3 N9 ]; D7 J
1748399 ALLEGRO_EDITOR     DATABASE      In release 17.2-2016, end caps not visible for certain clines in PCB Editor0 |7 \2 O: |  T# c0 X% R' L& z' F5 G6 e1 t: H
1748522 ALLEGRO_EDITOR     INTERACTIV    A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it% G: i) o* ]: q% B1 A, n! a1 s8 t7 w" e( V% B* ?
1734983 ALLEGRO_EDITOR     INTERFACES    Secondary step model does not stay mapped after drawing is reopened" G: o/ y3 S3 W% J( r! v5 ^
1753704 ALLEGRO_EDITOR     REFRESH       Refreshing symbols crashes PCB Editor0 z( R3 a, f2 g* q( p5 T6 Z7 D* Q
1493721 ALLEGRO_EDITOR     SHAPE         Voids on negative planes are not adhering to constraints# v1 ?- m( v% e
1711242 ALLEGRO_EDITOR     SHAPE         Route keep out leads to partly unfilled shapes with gaps* W' E' Z2 c6 K3 W) J1 [
! G: H3 @3 b6 a1726865 ALLEGRO_EDITOR     UI_GENERAL    Pop-up Mirror command does not mirror at cursor position: V' }! V: o6 c3 B8 b* k
+ A& u7 ~# t! n' c3 b1752987 ALLEGRO_EDITOR     UI_GENERAL    axlUIViewFileCreate zoom to xy location not working while in user created form.- b, A; _5 Z: U5 s+ o7 E3 o
1755638 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
& A. ]: {' p% V- U( a) [1719792 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC hangs or crashes PCB Editor
% Q$ ^7 {2 M0 r1624869 ALTM_TRANSLATOR    CAPTURE       A structure file is required to translate a third-party schematic to orcad Capture5 h) N& {5 y# @- h/ X) Q5 G1 S4 ?) O
1707416 ALTM_TRANSLATOR    CAPTURE       Missing components and pins in the OrCAD Capture schematic translated from a third-party tool- s( Z7 N/ k7 W
1708825 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate the schematic+ C9 ]1 Y, w4 s
* c- E+ A9 R  j9 e) W' h1719200 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate all the pages of a schematic
* a+ k+ Z# |$ B2 i1546070 ALTM_TRANSLATOR    CORE          Third-party to DE-HDL schematic translation fails4 B1 C. ]  f# |, ~) R8 P
' n8 O, p& `. g1700508 ALTM_TRANSLATOR    CORE          Third-party PCB translator does not work in release 17.2-2016
& ~7 ~4 W* _8 m" S! g1699340 ALTM_TRANSLATOR    DE_HDL        Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor6 D8 b; A/ p: m$ D
1630379 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator is not importing clines and vias+ M6 w# P. r% o4 N/ h
/ B' @* t  ]$ R  e! g1708615 ALTM_TRANSLATOR    PCB_EDITOR    All items of third-party PCB not imported in release 17.2-20165 K; p5 P) [( l; r* |: ~6 ^: ^
' K8 M$ x& k5 x, f2 y1758296 APD                DXF_IF        DXF OUT: Rounded rectangle pads mirrored incorrectly2 d; E  i% u/ |' o: I: {; J8 ]
1756040 APD                IMPORT_DATA   The 'die text in' command ignores values after the decimal point; p3 O7 w) ~/ K# ^; u7 ^- D* _- H7 n5 e5 t" T) n0 _# V
1727206 APD                SHAPE         Merging two shapes results in an incorrect shape. b7 j$ \$ h; f0 e+ r+ k0 a5 a' B
4 w  Z& J) K& V+ K1 L1753682 CONCEPT_HDL        CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL
$ |- R; g6 t8 ?, \1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic
, i' P: Q5 O; R% ~2 g' ]. V; A- {/ b; {0 X1747559 CONCEPT_HDL        CORE          Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)9 P' k2 i6 F, w) N% Y' b4 H; j
( Q% W7 p8 |- {1 d- i& z7 H/ K1749644 CONCEPT_HDL        CORE          In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes* Z, t. F6 o. o% a3 g4 h8 G2 w- V
1746910 CONCEPT_HDL        GLOBALCHANGE  Global Component Change unable to identify part data when using schematic pick option) g1 d% F: {9 T; v# V; J/ _  N! M/ R7 u2 t
1743572 FLOWS              PROJMGR       Project Manager displays incorrect values in Project Setting1 _1 M4 m; C, x: }1 X& g! H. ]4 x3 T2 m5 W! Y& q  m
1724124 FSP                DESIGN_EXPLOR Provide TCL command to filter design connectivity window) c! K1 Y' J3 Z1 C* \
& c3 f+ q# r7 [( ~7 \# I) |: z$ @1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner
0 c  W% U1 u% I6 C. U3 j1755750 PCB_LIBRARIAN      GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
1 ^8 ?& e4 D8 C+ w- q  o! z7 g1722993 PCB_LIBRARIAN      IMPORT_CSV    Part Developer crashes while importing part information stored in a .csv file# V, A  b0 p% h7 A  p; ?! B
5 j& p' p/ x$ y, g1758856 SIP_layout         3D_VIEWER     Correct the spelling error in the 3D Viewer Design Configuration window' m. x) g8 u0 Z; B) B* g$ {. y7 o3 `0 \( E0 X  c7 }& W
1755179 SIP_LAYOUT         ARTWORK       PCB Editor crashes when creating Gerber files# \8 x4 c0 g- o7 q& O
: b9 ?5 b0 a# |1743511 SIP_LAYOUT         MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check4 o+ B- q% W0 Q+ n* J
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发表于 2022-5-10 09:14:55 | 显示全部楼层
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