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分享:最新Hotfix_SPB17.20.022_wint_1of1补丁

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发表于 2017-6-30 08:36:09 | 显示全部楼层 |阅读模式
Fixed CCRs: SPB 17.2 HF022" R0 N7 @# w* X7 F$ P! `7 s
06-16-2017  o1 T; \5 U5 L: N2 Z! B+ `' T8 `- j+ q5 y* U
========================================================================================================================================================9 R2 ?; W% w4 Q3 O3 r
CCRID   Product            ProductLevel2 Title% k0 a9 ~. B+ ]" p6 B4 i, ^! J' k/ s5 i  K$ a  Z. u4 v$ F
========================================================================================================================================================9 [5 Y+ x, m: |1 h) L2 Z. e, s, z$ X9 ~0 z5 c  G& R: a
1755789 ADW                DBEDITOR      Checking in HSS Block returns 'Failed to create archive'
. b% P# e6 x* h; j# d9 D1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager2 D, w* b% E. B1 w" X& h2 s$ i6 |: p! e6 Z
* C+ U. K- W9 f4 {1 u7 i) h) o1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager
6 C3 l, I" _  U2 i! w+ V0 k& }1744081 ADW                FLOW_MGR      Error regarding configuration file when trying to open Workflow Manager5 l/ V8 [  a1 K* p- c
1756727 ADW                LIBIMPORT     EDM Library Import fails with java exceptions when merging classifications% q: e1 ~- b9 L9 g9 [' t: {
1743763 ADW                SRM           Find filter is grayed out when allegro PCB Editor is opened from EDM Flow Manager8 ?# [1 a. \+ N
1748399 ALLEGRO_EDITOR     DATABASE      In release 17.2-2016, end caps not visible for certain clines in PCB Editor0 |7 \2 O: |  T# c0 X! o4 ]( B9 f0 {& z1 T* T5 T! R9 B6 D
1748522 ALLEGRO_EDITOR     INTERACTIV    A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it% G: i) o* ]: q% B
: [- z; D1 e: g+ w" Y1734983 ALLEGRO_EDITOR     INTERFACES    Secondary step model does not stay mapped after drawing is reopened
; U4 W+ X! u1 L/ x1753704 ALLEGRO_EDITOR     REFRESH       Refreshing symbols crashes PCB Editor0 z( R3 a, f2 g
- u# \5 n* k- g  H5 x- i) e: f1493721 ALLEGRO_EDITOR     SHAPE         Voids on negative planes are not adhering to constraints
. u- K+ \# [+ l& n: r9 a1711242 ALLEGRO_EDITOR     SHAPE         Route keep out leads to partly unfilled shapes with gaps* W' E' Z2 c6 K3 W) J1 [
7 F( ~7 k' R* ?5 R1726865 ALLEGRO_EDITOR     UI_GENERAL    Pop-up Mirror command does not mirror at cursor position: V' }! V: o6 c3 B8 b* k, x3 g, w3 ]/ }7 m9 A
1752987 ALLEGRO_EDITOR     UI_GENERAL    axlUIViewFileCreate zoom to xy location not working while in user created form.& T" O! g. k$ s& R' A
1755638 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run: y1 m- T8 T2 z8 N8 k
1719792 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC hangs or crashes PCB Editor& m* r! a7 ?/ F6 L
1624869 ALTM_TRANSLATOR    CAPTURE       A structure file is required to translate a third-party schematic to orcad Capture5 h) N& {5 y# @
7 k) y" O4 Z8 p6 b" S: N4 ^1707416 ALTM_TRANSLATOR    CAPTURE       Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
% @/ o+ e2 v( Q1 x( S; K& n) L( n1708825 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate the schematic+ C9 ]1 Y, w4 s- `; s* t5 V$ t& |! |1 r5 G
1719200 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate all the pages of a schematic; S4 c4 ?, H; u' u/ v
1546070 ALTM_TRANSLATOR    CORE          Third-party to DE-HDL schematic translation fails4 B1 C. ]  f# |, ~) R8 P
+ D2 |. W8 [: s, b1700508 ALTM_TRANSLATOR    CORE          Third-party PCB translator does not work in release 17.2-2016
& J0 h, Q1 h2 r' Z( j9 W1 q1699340 ALTM_TRANSLATOR    DE_HDL        Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor( }( n3 {" m$ e" [; n) r) G) L
1630379 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator is not importing clines and vias+ M6 w# P. r% o4 N/ h
* M: l% W3 b: |' k) t8 a& _4 A1708615 ALTM_TRANSLATOR    PCB_EDITOR    All items of third-party PCB not imported in release 17.2-20165 K; p5 P) [( l; r* |: ~6 ^: ^
3 R" s* |( i1 O$ r5 m1758296 APD                DXF_IF        DXF OUT: Rounded rectangle pads mirrored incorrectly
' E, t4 T" @. M$ v2 T1756040 APD                IMPORT_DATA   The 'die text in' command ignores values after the decimal point; p3 O7 w) ~/ K# ^; u7 ^- D* _- H$ H$ O) Y: ]% ?" U/ q' @
1727206 APD                SHAPE         Merging two shapes results in an incorrect shape. b7 j$ \$ h; f0 e+ r+ k0 a5 a' B
" g9 Y5 f3 H% V' J7 ?1753682 CONCEPT_HDL        CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL1 W7 ?  |" m* q
1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic
3 }9 o1 t5 b! y- ]+ J1747559 CONCEPT_HDL        CORE          Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)9 P' k2 i6 F, w) N% Y' b4 H; j% l5 }$ @- l& s  s5 H1 I1 n: h5 P1 a
1749644 CONCEPT_HDL        CORE          In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes' j: g3 D9 c( A# _7 j: |
1746910 CONCEPT_HDL        GLOBALCHANGE  Global Component Change unable to identify part data when using schematic pick option) g1 d% F: {9 T; v# V; J
0 K' e; T& A+ Q, i$ o1743572 FLOWS              PROJMGR       Project Manager displays incorrect values in Project Setting1 _1 M4 m; C, x: }1 X& g! H. ]
# F* D( f% I8 {: a% q; A# _* z1724124 FSP                DESIGN_EXPLOR Provide TCL command to filter design connectivity window) c! K1 Y' J3 Z1 C* \) U4 Z+ E9 d/ E  Y3 z" \% j4 a  @
1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner
2 c3 r& K0 f0 r3 }3 R$ E0 @9 p  i" B1755750 PCB_LIBRARIAN      GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor  v+ l; c9 e4 w8 F' c% D9 F0 {
1722993 PCB_LIBRARIAN      IMPORT_CSV    Part Developer crashes while importing part information stored in a .csv file# V, A  b0 p% h7 A  p; ?! B
+ A8 j  K% W7 f1758856 SIP_layout         3D_VIEWER     Correct the spelling error in the 3D Viewer Design Configuration window' m. x) g8 u0 Z; B) B* g$ {
- q: N; N1 p. p& G" c* a3 M, {/ y1755179 SIP_LAYOUT         ARTWORK       PCB Editor crashes when creating Gerber files# \8 x4 c0 g- o7 q& O
3 [7 g/ v4 k0 }2 @; M1743511 SIP_LAYOUT         MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
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发表于 2022-5-10 09:14:55 | 显示全部楼层
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