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分享:最新Hotfix_SPB17.20.022_wint_1of1补丁

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发表于 2017-6-30 08:36:09 | 显示全部楼层 |阅读模式
Fixed CCRs: SPB 17.2 HF022) E1 E: V. K$ Y0 A
06-16-2017  o1 T; \5 U5 L: N2 Z! B
( W, w' f" u, t. i( w========================================================================================================================================================* v% g/ p7 Q1 ]# A; I3 b  _
CCRID   Product            ProductLevel2 Title% k0 a9 ~. B+ ]" p6 B
+ j+ v/ I& G/ s========================================================================================================================================================9 [5 Y+ x, m: |1 h) L2 Z. e, s4 j  E! c: P. M" Z6 H7 i/ h
1755789 ADW                DBEDITOR      Checking in HSS Block returns 'Failed to create archive'
. y( X" O+ M6 \5 h1731459 ADW                FLOW_MGR      Cannot open LRM from Flow Manager2 D, w* b% E. B1 w" X& h2 s$ i6 |: p! e6 Z- [' I" u# r" W) J! X+ Q9 z
1731460 ADW                FLOW_MGR      Cannot open LRM from Flow Manager) M8 H1 [+ A5 e7 i
1744081 ADW                FLOW_MGR      Error regarding configuration file when trying to open Workflow Manager
& x/ k) O) T: i* ]# ~8 s% c1756727 ADW                LIBIMPORT     EDM Library Import fails with java exceptions when merging classifications/ |4 R; i( a4 T2 `2 g1 D
1743763 ADW                SRM           Find filter is grayed out when allegro PCB Editor is opened from EDM Flow Manager# V7 n+ P8 ~2 A$ K. F6 f  ~4 N
1748399 ALLEGRO_EDITOR     DATABASE      In release 17.2-2016, end caps not visible for certain clines in PCB Editor0 |7 \2 O: |  T# c0 X2 R; s$ C+ C2 [% J4 S! X
1748522 ALLEGRO_EDITOR     INTERACTIV    A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it% G: i) o* ]: q% B6 w; p, ]! j  A* d! e1 s
1734983 ALLEGRO_EDITOR     INTERFACES    Secondary step model does not stay mapped after drawing is reopened
; d, n% C1 x$ j0 g1753704 ALLEGRO_EDITOR     REFRESH       Refreshing symbols crashes PCB Editor0 z( R3 a, f2 g
8 a1 g( B+ d, i5 ^0 b* G1493721 ALLEGRO_EDITOR     SHAPE         Voids on negative planes are not adhering to constraints
" x: Z' D; M* u1711242 ALLEGRO_EDITOR     SHAPE         Route keep out leads to partly unfilled shapes with gaps* W' E' Z2 c6 K3 W) J1 [
) _1 g* a; Z' D; Y, {* A1726865 ALLEGRO_EDITOR     UI_GENERAL    Pop-up Mirror command does not mirror at cursor position: V' }! V: o6 c3 B8 b* k/ U* I) y" ]+ @5 B
1752987 ALLEGRO_EDITOR     UI_GENERAL    axlUIViewFileCreate zoom to xy location not working while in user created form.
2 o5 a) A; u0 n1755638 ALLEGRO_EDITOR     UI_GENERAL    In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
3 t/ T% N' \3 @- ~& R3 E1719792 ALLEGRO_PROD_TOOLB CORE          Productivity Toolbox Z-DRC hangs or crashes PCB Editor
+ H& T: [" w0 N! t4 e1624869 ALTM_TRANSLATOR    CAPTURE       A structure file is required to translate a third-party schematic to orcad Capture5 h) N& {5 y# @3 ?, K; j/ k0 K+ r
1707416 ALTM_TRANSLATOR    CAPTURE       Missing components and pins in the OrCAD Capture schematic translated from a third-party tool
$ a* V9 c0 X( {+ C/ F' P1708825 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate the schematic+ C9 ]1 Y, w4 s
* ^( Q2 q8 J: H1 ]4 t( Z1719200 ALTM_TRANSLATOR    CAPTURE       The third-party translator fails to translate all the pages of a schematic
' m  g+ ]- Q. v$ b1 Z# M1546070 ALTM_TRANSLATOR    CORE          Third-party to DE-HDL schematic translation fails4 B1 C. ]  f# |, ~) R8 P
% b6 [6 ~3 ]( H0 G( u# _0 _$ g1700508 ALTM_TRANSLATOR    CORE          Third-party PCB translator does not work in release 17.2-2016# n1 {& s1 q( f0 E
1699340 ALTM_TRANSLATOR    DE_HDL        Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor
% m; n& ?- C5 q0 v, \! O1630379 ALTM_TRANSLATOR    PCB_EDITOR    Third-party translator is not importing clines and vias+ M6 w# P. r% o4 N/ h- P4 h3 \9 O( Q: [  z: _
1708615 ALTM_TRANSLATOR    PCB_EDITOR    All items of third-party PCB not imported in release 17.2-20165 K; p5 P) [( l; r* |: ~6 ^: ^
. \0 K$ V5 x( Z7 i# ~; I  i; o1758296 APD                DXF_IF        DXF OUT: Rounded rectangle pads mirrored incorrectly- `  n8 `. F% W1 ^0 a: s
1756040 APD                IMPORT_DATA   The 'die text in' command ignores values after the decimal point; p3 O7 w) ~/ K# ^; u7 ^- D* _- H
8 G. ~1 j  F1 E# W+ Z  T' ^1727206 APD                SHAPE         Merging two shapes results in an incorrect shape. b7 j$ \$ h; f0 e+ r+ k0 a5 a' B
3 E3 j8 D) P. i1753682 CONCEPT_HDL        CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL; u1 r8 |$ }! b# ^7 H5 T
1721334 CONCEPT_HDL        CORE          dsreportgen not able to resolve gated part on schematic
9 s, [3 ^% T% @, m1747559 CONCEPT_HDL        CORE          Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)9 P' k2 i6 F, w) N% Y' b4 H; j1 N# t, J! f* Q/ {
1749644 CONCEPT_HDL        CORE          In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes4 E1 c0 P! a8 y( H0 B
1746910 CONCEPT_HDL        GLOBALCHANGE  Global Component Change unable to identify part data when using schematic pick option) g1 d% F: {9 T; v# V; J( U! q% A2 b1 Z+ ~7 L' }
1743572 FLOWS              PROJMGR       Project Manager displays incorrect values in Project Setting1 _1 M4 m; C, x: }1 X& g! H. ]
: R" i! `# K3 A& ~) W1724124 FSP                DESIGN_EXPLOR Provide TCL command to filter design connectivity window) c! K1 Y' J3 Z1 C* \
) h: |  ]# H3 Q& c# I3 ^5 l3 k1719105 FSP                GUI           Tabular sorting not working in FPGA System Planner% w2 }5 w5 L: ]; ^) R+ Q8 {
1755750 PCB_LIBRARIAN      GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
6 I5 g$ b7 z/ J" _1722993 PCB_LIBRARIAN      IMPORT_CSV    Part Developer crashes while importing part information stored in a .csv file# V, A  b0 p% h7 A  p; ?! B7 d: b6 w7 D: N' J  ~" h
1758856 SIP_layout         3D_VIEWER     Correct the spelling error in the 3D Viewer Design Configuration window' m. x) g8 u0 Z; B) B* g$ {! X- _0 n. n! u3 l0 D. n8 |. f
1755179 SIP_LAYOUT         ARTWORK       PCB Editor crashes when creating Gerber files# \8 x4 c0 g- o7 q& O4 Y! {0 n7 S  a$ T+ i9 W2 ~
1743511 SIP_LAYOUT         MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check
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发表于 2022-5-10 09:14:55 | 显示全部楼层
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