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本帖最后由 深圳-绿皮 于 2013-11-22 10:14 编辑 . n$ G8 i; L1 I9 z B
; S J0 O( v: c" Z7 tDATE: 11-15-2013 HOTFIX VERSION: 019. K* i, p0 V3 {. h& F
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- X0 W M" j$ j* O1176155 CONCEPT_HDL CORE Graphics remnants with 16.6 QIR 3
! Z: Q5 Y K9 H9 G7 W1178272 CONCEPT_HDL OTHER Verilog netlist does not include split blocks correctly9 e* i! _% ~5 o7 N5 n5 p( ] q
1190782 FSP FPGA_SUPPORT Support for Altera > 5SGXEA9N2F45 device.
- o1 u/ G) h, H5 R9 Z. m6 x1194140 ADW LRM SYNC_PROPERTIES is not resolving issues a based sync_properties settings
8 B0 W& g3 S6 P, |- p1195744 APD EDIT_ETCH Diff_Pair routing fails on certain Uvias in the pair.5 e7 K9 l5 A) e
1196704 allegro_EDITOR INTERFACES ENH: During ipc2581 export checkboxes corresponding to 縈iscellaneous Image Layers� should automatically get selected
. }0 E Q. v+ f# g& |/ Z7 `. Q1198340 ALLEGRO_EDITOR OTHER Multiple -product option on the Allegro command line does not access the second -product( _5 [( g( Z1 T
1198596 ALLEGRO_EDITOR INTERFACES When copper thickness is increased for the outer layers, step Viewer does not show correct component position.
3 p7 I, U8 j4 y+ b- m/ D1199673 PCB_LIBRARIAN OTHER Component Browser fails to load footrpints if they are set with UNC path+ \8 C+ T) O8 z K$ `
1199889 ALLEGRO_EDITOR DATABASE Allegro crashing with latest hotfix.
# N. q. Z9 U) q1200303 ALLEGRO_EDITOR GRAPHICS 3D Viewer does not update after changing STEP model mapping
/ r8 _$ W; W; C: u( u1200449 ALLEGRO_EDITOR REPORTS Allegro crashes when generating Net Loop Report.
2 R7 u8 P- p$ H% d \1200915 ALLEGRO_EDITOR DATABASE Reducing accuracy of this specific design crashes Allegro
) {+ G% ]" x$ P- W# R$ C! @1201011 ADW COMPONENT_BROWSE Component Browser crashes in DB mode
; k' _6 {' G3 V4 d: p6 N1201376 ALLEGRO_EDITOR INTERFACES Allegro hangs when trying to map a specific STEP model to a package drawing.7 [% Y/ c0 s7 z1 u3 ?
1201897 SIP_layout IMPORT_DATA BGA Pin Colors not matching the Colors defined in the Symbol Spreadsheet after updating.# [% K" a, q# Q& {
1202709 ALLEGRO_EDITOR INTERFACES STEP File generated from Allegro is not overwritten when the variable "set ads_textrevs
1 p9 A* {. ~2 _8 _" c1202820 ALLEGRO_EDITOR INTERFACES Different xml generation for same step model on S106 and S0175 F M' A0 S# w. H3 \8 c
1202842 ALLEGRO_EDITOR INTERFACES Step model invisible for one pin dra in allegro 16.6 symbol editor; N9 s; q& W3 s
1202983 ALLEGRO_EDITOR SHAPE Shape voiding creates DRC with Route Keepout- Y* X* R" _& _/ y9 e$ ^3 }
1203125 ALLEGRO_EDITOR OTHER Exporting STEP file with External copper enabled does not show all copper when viewed with Solid Edge or Inventor
. ?2 }/ x4 X" L2 W, y1203236 ALLEGRO_EDITOR INTERFACES IPC2581 output with crosshatched shape is not correct
7 Q) K9 e& E. l5 o* D6 X1203995 CONCEPT_HDL CHECKPLUS CheckPlus rule, local_signal_no_offpage_body, getting an incorrect failure.
: S' z2 \; C9 x( G1204629 ALLEGRO_EDITOR SKILL axlUIDataBrowse crashes the editor or returns error
7 L. S" e n c2 n: c c3 r1204640 SIP_LAYOUT DIE_EDITOR Concurrent co-design update fails
1 I' _! H4 {" \% J# J$ g3 ]1204881 SIP_LAYOUT BGA_GENERATOR Pin numbers are messed up after deleting a pin at a staggered bga
. t. H8 T3 s0 H: g2 l9 k! _) e1204885 CONCEPT_HDL CONSTRAINT_MGR Cant assign discrete models after the wrong model was removed.! X7 l% w1 k( O9 D2 s3 Q; ]# ~
1205374 ALLEGRO_EDITOR OTHER pdf out command creates incorrect drill Symbol Characters placement in pdf file when setting film mirrored.
; c& Q1 c9 v( O3 s4 ^1205729 SIP_LAYOUT DIE_EDITOR update of codesign db fails on exit from die editor
8 Q! I; p" Z) _, U: A4 ^4 v# J, g, u" Q! c1205801 ALLEGRO_EDITOR OTHER Tool crash when do export IPF.3 s- }4 t) i8 H; E. K0 j- d
1205881 CONSTRAINT_MGR OTHER In CMGR , Objects > Create crashes Allegro0 \& n1 \. h$ _9 G" [
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6 x# [+ ?8 |3 S5 Q0 X; Ihttp://pan.baidu.com/s/13S6yr
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