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27号补丁修复的BUG较多!
6 X& e: k, U. q4 X U) t百度网盘下载链接http://pan.baidu.com/s/1mgwSsPy
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9 m. {6 z# {/ C3 BDATE: 04-25-2014 HOTFIX VERSION: 027) Z0 t4 W! J$ H6 a" y0 l& v
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( }9 g+ \8 u" T7 j* pCCRID PRODUCT PRODUCTLEVEL2 TITLE1 X- p, n# D$ \8 d0 i6 z
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/ g, h6 \+ Q1 W9 F0 [. b8 k; @308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM5 Z# Z a0 L+ z- o0 a/ A1 y
481674 allegro_EDITOR pads_IN No board file saved from pads_in' n& h0 i9 g" d
982929 allegro_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.
( O, u" M2 }6 u' ]1012783 FSP OTHER Need Undo Command in FSP
: d- s6 M3 m( p" P1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.5 z: F0 b' R# j% o6 u+ e
1072673 pcb_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved. m5 k& s9 @/ I! f% s8 o" J6 G% ^
1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
3 X! \. G6 N8 ~0 X' r1 W6 X1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
4 j4 j; M0 d' Y' K1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
0 X* b2 g5 U5 F! |1 r5 t1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command+ N) R7 t5 w9 y( M
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode* |6 _0 W% i& J( X* N# i) B9 v6 U
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present% X& F; b. y- v' Z
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.6 A' i A! v( z: W, Z+ v9 j
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings. P, _ W1 c) s S* x: e! c. S
1185575 SIP_layout DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.9 P/ P7 r% g1 O+ K' ~4 [& C
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV
2 S, P" p) U { i1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
( U* R2 Y/ O3 j; C' x9 P/ M% o1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
* O* X9 H8 w, {7 ]) W1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime0 P% x7 Y% |+ q+ C7 O7 e
1208478 PSPICE PROBE Attached project gives overflow error with marching ON.
& l. s. o0 [& r" Z1 Y1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol9 `1 u# w/ z0 n4 k
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
; n# v; y9 y; \0 A) A1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
$ d9 \! a2 x( _5 X2 h1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
8 O$ e! E0 L( Z- F6 q1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?0 U: i! Z( N+ S% ?9 s; {9 e$ `9 S
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.2 f, H8 ]6 _ W' X4 y7 _
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values5 y. F4 k' z! P( k. \+ f7 `, ^
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
7 i7 V- Y% V+ O# ?: m1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information6 S* h3 z; c i2 L+ J, u# |$ l
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
9 D2 P6 I; x: i, Z8 f) i# W3 T9 ^+ E1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
" R4 k* x- h* w$ u1 N1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes, q% l0 a' r/ u4 i V7 D
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux3 \" r- p/ C" e
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
3 t0 p$ ~# p( J+ x2 c1 P7 p1221182 ADW TDA Team Design with SAMBA* r% O5 p g0 {$ ^1 R; @, y, ]) R
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair7 M3 g7 ~; o D/ _' ~2 S
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
) |3 a6 H7 w& r1 M! A1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?7 C, Z, {( E4 \
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts, w$ @5 P: ?( I8 Y( x; d+ M
1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
2 d* g* j/ o8 a6 t* L; h! R1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.- u" }- N. d6 v) n) ?
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
" c1 Z8 i& {0 n, y1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.! F0 x5 O/ s: m
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
{, ~9 N) o8 J3 q4 C. v1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
2 N. C2 H$ m* R( a, I% R1225494 CAPTURE DRC Different DRC results for Entire design and selection: G# }* H! a* r
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property3 s6 b7 _4 S9 B3 h9 W
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
3 q7 s' K6 g9 ?/ Y: q& Y4 l1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet% n d* R3 q [1 X' m) Q
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
3 h' m& A, L* g/ c& ^1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
. L" w: Y, j! D6 s1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors0 U/ E* X) @2 O& k7 p
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,81 k [ \: {9 W O5 Q
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
# Q, L# q% O! s: ?. _: l3 s1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part% |+ a) l" i1 j1 o
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case, ^; o; g# ]1 k1 [% a4 S
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
( {: {% s& A4 O' ^1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
/ z' S- @: Z8 P1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.& q8 y$ N1 L0 w$ w7 Y
1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.: K: }. ]- K- M3 ]7 u; I
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
- m4 E- @5 A+ a. e( O- t) h1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
$ | w0 f8 w# d' B/ h, e1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
0 E8 x; G) i# C) }( L+ M2 y0 @1230432 CONCEPT_HDL CORE No Description information in BOM
$ Z) j/ P0 p* ?1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes7 f$ G8 ?5 S+ H* F( _. s" ?9 E
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files
! t1 C9 m" D4 g8 j9 ?1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
M7 s( K% t8 y- e8 W4 d. ^1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets) [% f. ?" C6 R$ x; y2 F
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.% H# T- q- j0 U& c; y
1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode& o2 {, ] o$ U$ {' k, B' X C& {7 ]
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical ?: W' L( I" W# \
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode( h/ u" u, j5 ^ n5 o/ o
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files0 P7 ?) u6 _9 J# v6 i1 l* i
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy
2 x4 o& _! F3 C" P1 [1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
- Y7 Q8 t' |/ v7 E9 { E7 X% ^9 f3 h1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect/ V% }7 {8 ~2 h5 ~ U# b) B: C7 c
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set3 T, H! b9 d- @
1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
x4 ]5 Y! F6 p1 q- K1236161 CONCEPT_HDL CORE Import Design shows the current project pages
7 g2 a7 _" I8 R# g4 G1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.% `" o# e9 i9 N; \( g
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion0 k& y$ k% B3 {) y$ z! \) v, C" u$ z
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
; U' \: @& {( ~( G$ ^1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape) ~# U4 O; {& d- C6 R$ x
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming* A: N! n- N8 U% _' Y
1236781 F2B PACKAGERXL Export Physical produces empty files
" t/ G3 f+ j( Q/ ^1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run8 \5 S% W3 x, a0 Q- y9 E
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command' I+ Z \ I/ e4 Z
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
5 e9 d, M+ }' s# e+ n5 c9 G1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
5 r5 M$ i7 l2 r+ e" G1 r1238852 CAPTURE GENERAL signal list not updated for buses
/ \. u9 _! Y# Q0 X" j) w8 y& A8 C1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
+ `# k* r& O. d$ N) i1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
3 `1 _4 @- B, O* s v1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE0 e* }# s7 u# \) h
1239763 PSPICE PROBE Cannot modify text label if right y axis is active
, |0 `/ I; o7 |* P. I: v1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
. [ G& c0 y% |/ @4 g1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.2 X0 A' J( f( v# b2 e, F
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing3 \8 W5 j$ {3 C" a% J( e" ?: q
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file
0 t% {: h+ w3 ^ `1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
9 y" r4 }, E& V9 M) v- |9 ]% s: m1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
) e& p& g3 G7 b ]7 |' d1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms$ _. |- C) }- c3 g8 e7 f/ N
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working0 S7 g9 q3 |6 Y& U
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.0 Q2 j% V7 h3 C4 @
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard0 a- J: y% l4 t# X9 x
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning* `, ?# t9 o' Y
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
9 C# h" r( n! [& a/ `1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer! j$ b8 j% _, C/ A9 X; ~7 W* H4 j
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results
6 [! `, r) @0 }# Q: u1243609 CONCEPT_HDL CORE autoprop for occurrence properties
; V( L6 Q" E V' T6 b3 F7 }1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
5 w8 Q% v- O3 c1 E) ?2 W' d% j1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.' ?$ D" r& N' Z
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring& H4 o1 z$ k8 J2 ]8 q6 G. f
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
6 }' p; I; q0 I& h1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is, v; l6 ~# H' O0 w
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
' \1 |: H" P% \/ ~+ `2 ~1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
* s+ Q `' ]! A0 ~3 d# x4 `& @+ p1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character; T0 h; e" W3 Z, X, _5 m: W
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters k$ ]2 V5 F4 Y( \/ u
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown6 |$ f" |4 F8 ]% n! U
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number4 c$ p3 Y$ j. o# P' X
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
3 B4 B) q, n( S1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
' B9 d o1 q3 z! I8 F1247462 CONCEPT_HDL CORE Text issue while moving with bounding box: I) J) g, W2 s6 g5 t
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
9 j; D* }+ G6 D1 X! t3 ~( p$ q1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
! R9 g7 T0 r6 M, l% S) t" H1 b$ O1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts
7 L7 b& w/ s+ ^: N/ |) G1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
& F0 A1 r# C, @1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint5 Z+ m0 C- J! ]+ ^8 {
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly' y6 l0 o: L" F& f9 \& _
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.7 ~& f, D! U+ w- a) T6 _
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
+ j, l$ f6 ~3 _! k$ \7 Z( x! E6 n$ l1253424 SCM SCHGEN Export Schematics Crashes System Architect
/ F+ x: f" j& ~. r; }7 _1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled5 ~* v, S: ?1 E" } o& e
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
7 w" U) z* B y+ ^+ W! [# D( N1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router0 [2 I5 \/ f' z# G& J# {! S" _* p
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
: }, v% V |5 j+ R$ c1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.0 v" H J; r: i4 M9 \/ \
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation8 r/ i" [% q2 @3 _* U" k
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects
! h6 H7 f' k, x h4 q! w1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode6 H, ]/ F, L) J
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided& e3 t& [2 P9 ?. l# d! ?
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
* O$ R( [# R3 A* G: b1 q1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool2 g- D" P- q! v7 z1 c' Y- N
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
; _+ V: a7 ?. f1 d1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library( D5 v( h# L/ \5 A2 n( t
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
: c& t$ M b5 ?/ H0 r* F$ h3 e) ?' ?0 \3 M1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash; r! q$ H" b6 ?+ i& i2 W- d2 r
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
6 j/ n" h+ e; |- f8 S4 V+ x1258029 APD WIREBOND The bondwire lost after import the wire information) @& M. a1 D" f1 u% e* b3 l
1258979 APD NC NC Drill: There is difference of number of drills.
& D7 _$ E: x( ^- {7 o. O$ ]1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement
6 t/ r3 r% C( v# V# u. f1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.3 @4 ^( H* U, v* ]& d4 \
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"; {/ g0 T# u8 X! g2 s1 ^9 m
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines+ \0 ^: M9 A) q1 s, _
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
; ^/ W, I, l) [$ Y$ \1 ?1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss" {, j4 w! a8 E i8 H* d9 H1 B
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